CY7C67300_07 Datasheet, PDF (24/98 Pages) Cypress Semiconductor – EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support

CY7C67300
Extended Page n Map Register [R/W]
• Extended Page 1 Map Register 0xC018
• Extended Page 2 Map Register 0xC01A
Figure 20. Extended Page n Map Register
Bit #
15
14
13
12
11
10
9
8
Field
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register Description
The Extended Page n Map register contains the Page n
high-order address bits. These bits are always appended to
accesses to the Page n Memory mapped space.
Address (Bits [15:0])
The Address field contains the high-order bits 28 to 13 of the
Page n address. The address pins [8:0] (Page n address
[21:13]) reflect the content of this register when the CPU
accesses the address 0x8000-0x9FFF. For the SRAM mode,
the address pin on [4:0] (Page n address [17:13]) is used.
Set bit [8] (Page n address [21]) to ‘0’, so that Page n
reads/writes access external areas (SRAM, ROM or periph-
erals). nXMEMSEL is the external chip select for this space.
Upper Address Enable Register [0xC038] [R/W]
Figure 21. External Memory Control Register
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
X
X
X
X
X
X
X
X
Bit #
7
Field
Read/Write
-
Default
X
6
5
Reserved
-
-
X
X
4
3
2
1
0
Upper
Address
Enable
Reserved
-
R/W
X
0
X
X
X
Register Description
The Upper Address Enable register enables/disables the four
most significant bits of the external address A[18:15]. This
register defaults to having the Upper Address disabled. Note
that on power up, pins A[18:15] are driven high.
Upper Address Enable (Bit 3)
The Upper Address Enable bit enables/disables the four most
significant bits of the external address A[18:15].
1: Enable A[18:15] of the external memory interface for
general addressing.
0: Disable A[18:15], not available.
Reserved
Write all reserved bits with ’0’.
Document #: 38-08015 Rev. *H
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