CY7C67300_07 Datasheet, PDF (2/98 Pages) Cypress Semiconductor – EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support

CY7C67300
Introduction
EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first
full-speed, low cost multiport host/peripheral controller.
EZ-Host is designed to easily interface to most high perfor-
mance CPUs to add USB host functionality. EZ-Host has its
own 16-bit RISC processor to act as a coprocessor or operate
in standalone mode. EZ-Host also has a programmable IO
interface block allowing a wide range of interface options.
Functional Overview
An overview of the processor core components are presented
in this section.
Interrupts
EZ-Host provides 128 interrupt vectors. The first 48 vectors
are hardware interrupts and the following 80 vectors are
software interrupts.
General Timers and Watchdog Timer
EZ-Host has two built in programmable timers and a Watchdog
timer. All three timers can generate an interrupt to the EZ-Host.
Power Management
EZ-Host has one main power saving mode, Sleep. Sleep
mode pauses all operations and provides the lowest power
state.
Processor Core
EZ-Host has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
Clocking
EZ-Host requires a 12 MHz source for clocking. Either an
external crystal or TTL level oscillator may be used. EZ-Host
has an internal PLL that produces a 48 MHz internal clock from
the 12 MHz source.
Memory
EZ-Host has a built in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-Host BIOS.
The internal RAM can be used for program code or data.
Interface Descriptions
EZ-Host has a wide variety of interface options for connec-
tivity. With several interface options available, EZ-Host can act
as a seamless data transport between many different types of
devices.
See Table 1 and Table 2 on page 3 to understand how the
interfaces share pins and which can coexist. Note that some
interfaces have more then one possible port location
selectable through the GPIO control register [0xC006].
General guidelines for interfaces are as follows:
• HPI and IDE interfaces are mutually exclusive.
• If 16-bit external memory is required, then HSS and SPI
default locations must be used.
• I²C EEPROM and OTG do not conflict with any interfaces.
Table 1. Interface Options for GPIO Pins
GPIO Pins
GPIO31
GPIO30
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
HPI
INT
nRD
nWR
nCS
A1
A0
D15
D14
D13
D12
D11
IDE
PWM
IOREADY
IOR
IOW
CS1
CS0
A2
A1
A0
D15
D14
D13
D12
D11
PWM3
PWM2
PWM1
PWM0
HSS
SPI
CTS^[1]
RTS^[1]
RXD^[1]
TXD^[1]
MOSI^[1]
UART
TX
RX
I2C
SCL/SDA
SCL/SDA
OTG
OTGID
Note
1. Default interface location.
Document #: 38-08015 Rev. *H
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