CYV15G0104TRB Datasheet, PDF (23/28 Pages) Cypress Semiconductor – Independent Clock HOTLink II™ Serializer and Reclocking Deserializer

CYV15G0104TRB
CYV15G0104TRB HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface
Write Timing
REFCLKB selected
TXRATEB = 1
t_REFH
t_REFCLK
t_REFL
REFCLKB
Note 27
t_TREFDS
t_TREFDH ^tTREFDS
TXDB[9:0]
Transmit Interface
TXCLKOB Timing
TXRATE = 1
REFCLKB
TXCLKOB
(internal)
Note 29
Transmit Interface
TXCLKOB Timing
TXRATEB = 0
REFCLKB
TXCLKOB
Note29
t_REFH
t_TXCLKO
t_REFCLK
Note 28
t_REFCLK
t_REFH
Note28
t_REFL
t_TXCLKO
t_REFL
t_TREFDH
Notes
27. When REFCLKB± is configured for half-rate operation (TXRATEB = 1) and data is captured using REFCLKB instead of a TXCLKB clock. Data is captured using
both the rising and falling edges of REFCLKB.
28. The TXCLKOB output remains at the character rate regardless of the state of TXRATEB and does not follow the duty cycle of REFCLKB±.
29. The rising edge of TXCLKOB output has no direct phase relationship to the REFCLKB± input.
Document #: 38-02100 Rev. *C
Page 23 of 28
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