CYV15G0104TRB Datasheet, PDF (12/28 Pages) Cypress Semiconductor – Independent Clock HOTLink II™ Serializer and Reclocking Deserializer

CYV15G0104TRB
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the TRGCLKA±
input. If the VCO is running at a frequency beyond
±1500ppm^[24] as defined by the TRGCLKA± frequency, it is
periodically forced to the correct frequency (as defined by
TRGCLKA±, SPDSELA, and TRGRATEA) and then released
in an attempt to lock to the input data stream.
The sampling and relock period of the Range Control is calcu-
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKA±, the LFIA output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIA should be
HIGH.
The operating serial signaling-rate and allowable range of
TRGCLKA± frequencies are listed in Table 3.
Table 3. Operating Speed Settings
SPDSELA TRGRATEA
LOW
1
0
MID (Open)
1
0
HIGH
1
0
TRGCLKA±
Frequency
(MHz)
reserved
19.5–40
20–40
40–80
40–75
80–150
Signaling
Rate (Mbps)
195–400
400–800
800–1500
Receive Channel Enabled
The receive channel can be enabled or disabled through the
RXPLLPDA input latch as controlled by the device configu-
ration interface. When RXPLLPDA = 0, the CDR PLL and
analog circuitry of the channel are disabled. Any disabled
channel indicates a constant link fault condition on the LFIA
output. When RXPLLPDA = 1, the CDR PLL and receive
channel are enabled to receive a serial stream.
Note. When the disabled receive channel is reenabled, the
status of the LFIA output and data on the parallel outputs for
the associated channel may be indeterminate for up to 2 ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from the
received serial stream is performed by a separate CDR block
within the receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of
the transitions in the incoming bit stream and aligns the phase
of the internal bit-rate clock to the transitions in the selected
serial data stream.
Each CDR accepts a character-rate (bit-rate ÷ 10) or
half-character-rate (bit-rate ÷ 20) training clock from the
TRGCLKA± input. This TRGCLKA± input is used to
• ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit-rate)
• reduce PLL acquisition time
• limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signaling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks TRGCLKA± instead of the
data stream. Once the CDR output (RXCLKA±) frequency
returns back close to the TRGCLKA± frequency, the CDR
input is switched back to the input data stream. If no data is
present at the selected line receiver, this switching behavior
may result in brief RXCLKA± frequency excursions from
TRGCLKA±. However, the validity of the input data stream is
indicated by the LFIA output. The frequency of TRGCLKA± is
required to be within ±1500ppm^[24] of the frequency of the
clock that drives the REFCLKB± input of the remote trans-
mitter to ensure a lock to the incoming data stream. This large
ppm tolerance allows the CDR PLL to reliably receive a 1.485
or 1.485/1.001 Gbps SMPTE HD-SDI data stream with a
constant TRGCLK frequency.
For systems using multiple or redundant connections, the
LFIA output can be used to select an alternate data stream.
When an LFIA indication is detected, external logic can toggle
selection of the INA1± and INA2± input through the INSELA
input. When a port switch takes place, it is necessary for the
receive PLL for that channel to reacquire the new serial
stream.
Reclocker
The receive channel performs a reclocker function on the
incoming serial data. To do this, the Clock and Data Recovery
PLL first recovers the clock from the data. The data is retimed
by the recovered clock and then passed to an output register.
Also, the recovered character clock from the receive PLL is
passed to the reclocker output PLL which generates the bit
clock that is used to clock the retimed data into the output
register. This data stream is then transmitted through the
differential serial outputs.
Reclocker Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
reclocker output register in the reclocker channel. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Reclocker Output Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both
reclocker serial drivers are in this disabled state, the internal
Document #: 38-02100 Rev. *C
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