CY8C20XX7 Datasheet, PDF (23/43 Pages) Cypress Semiconductor – 1.8 V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors

AC Programming Specifications
Figure 10. AC Waveform
CY8C20xx7/S
SCLK (P1[1])
SDATA (P1[0])
T _{RSCL K}
T _{FSCL K}
T_SSCLK
T _{HSCL K}
T_DSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC Programming Specifications
Symbol
t_RSCLK
t_FSCLK
t_SSCLK
t_HSCLK
F_SCLK
t_ERASEB
t_WRITE
t_DSCLK
t_DSCLK3
t_DSCLK2
t_XRST3
t_XRES
t_VDDWAIT[38]
t_VDDXRES[38]
t_POLL
t_ACQ[38]
t_XRESINI[38]
Description
Rise time of SCLK
Fall time of SCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
External reset pulse width after power-up
XRES pulse length
V_DD stable to wait-and-poll hold off
V_DD stable to XRES assertion delay
SDAT high pulse time
“Key window” time after a V_DD ramp
acquire event, based on 256 ILO clocks.
“Key window” time after an XRES event,
based on 8 ILO clocks
Conditions
–
–
–
–
–
–
–
3.6  V_DD
3.0  V_DD  3.6
1.71  V_DD  3.0
Required to enter programming
mode when coming out of sleep
–
–
–
–
–
–
Min
1
1
40
40
0
–
–
–
–
–
300
300
0.1
14.27
0.01
3.20
98
Typ Max Units
–
20
ns
–
20
ns
–
–
ns
–
–
ns
–
8
MHz
–
18
ms
–
25
ms
–
60
ns
–
85
ns
–
130
ns
–
–
s
–
–
s
–
1
ms
–
–
ms
–
200
ms
– 19.60 ms
–
615
s
Note
38. Valid from 5 to 50 °C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67,
CY8C20X47, CY8C20X37, Programming Spec for more details.
Document Number: 001-69257 Rev. *I
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