CY8C20XX7 Datasheet, PDF (2/43 Pages) Cypress Semiconductor – 1.8 V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors

CY8C20xx7/S
Logic Block Diagram
PSoC CORE
Port 4 Port 3
Port 2
Port 1
Port 0
1.8/2.5/3 V
LDO
PWRSYS _[2]
(Regulator)
SYSTEM BUS
Global Analog Interconnect
1K/2 K
SRAM
Interrupt
Controller
Supervisory ROM (SROM)
8K/16K/32 K Flash
Nonvolatile Memory
CPU Core(M8C)
Sleep and
Watchdog
6/12/ 24 MHz Internal Main Oscillator
( IMO)
Internal Low Speed Oscillator ( ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Comparator #1
Comparator #2
SYSTEM BUS
CapSense
Module
Analog
Reference
Analog
Mux
I2C
Slave
Internal
Voltage
References
System
Resets
POR
and
LVD
SPI
Master/
Slave
SYSTEM RESOURCES
Three 16- Bit
Programmable
Timers
Digital
Clocks
Note
2. Internal voltage regulator for internal circuitry
Document Number: 001-69257 Rev. *I
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