CY7C9689A Datasheet, PDF (23/46 Pages) Cypress Semiconductor – TAXI-compatible HOTLink Transceiver

CY7C9689A
CY7C9689A Receiver TTL Switching Characteristics, FIFO Enabled Over the Operating Range
Parameter
f_RIS
t_RXCLKIP
t_RXCPWH
t_RXCPWL
t_RXCLKIR[16]
t_RXCLKIF[16]
t_RXENS
t_RXENH
t_RXRSS
t_RXRSH
t_RXCES
t_RXCEH
t_RXA
t_RXZA
t_RXOE
t_RXZA
Description
RXCLK Clock Cycle Frequency With Receive FIFO Enabled
RXCLK Input Period
RXCLK Input HIGH Time
RXCLK Input LOW Time
RXCLK Input Rise Time^[18]
RXCLK Input Fall Time^[18]
Receive Enable Set-up Time to RXCLK↑
Receive Enable Hold Time from RXCLK↑
Receive FIFO Reset (RXRXT) Set-up Time to RXCLK↑
Receive FIFO Reset (RXRXT) Hold Time from RXCLK↑
Receive Chip Enable (CE) Set-up Time to RXCLK↑
Receive Chip Enable (CE) Hold Time from RXCLK↑
Flag and Data Access Time From RXCLK↑ to Output
Sample of CE LOW by RXCLK↑, Output High-Z to Active HIGH or LOW,^[19]
or Sample of RXEN Asserted by RXCLK↑, Output High-Z to Active HIGH or LOW
Sample of CE LOW by RXCLK↑ to Output Valid,^[19]
or Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs Valid
Sample of CE HIGH by RXCLK↑ to Output in High-Z,^[19]
or Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs in High-Z
Min.
20
6.5
6.5
0.7
0.7
4
1
4
1
4
1
1.5
0
1.5
1.5
Max.
50
5
5
15
20
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CY7C9689A Transmitter TTL Switching Characteristics, FIFO Bypassed Over the Operating Range
Parameter
Description
Min.
Max. Unit
t_TRA
Flag Access Time From REFCLK↑ to Output
2
t_REFDS
Write Data Set-up Time to REFCLK↑
4
t_REFDH
Write Data Hold Time from REFCLK↑
2
t_REFENS
Transmit Enable Set-up Time to REFCLK↑
4
t_REFENH
Transmit Enable Hold Time from REFCLK↑
2
t_REFCES
Transmit Chip Enable (CE) Set-up Time to REFCLK↑
4
t_REFCEH
Transmit Chip Enable (CE) Hold Time from REFCLK↑
2
t_REFZA
Sample of CE LOW by REFCLK↑, Output High-Z to Active HIGH or LOW
0
t_REFOE
Sample of CE LOW by REFCLK↑ to Flag Output Valid
1.5
t_REFAZ
Sample of CE HIGH by REFCLK↑ to Flag Output High-Z
1.5
15
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
20
ns
CY7C9689A Receiver TTL Switching Characteristics, FIFO Bypassed Over the Operating Range
Parameter
f_ROS[20]
Description
RXCLK Clock Output Frequency—100 to 200 MBaud 8-bit Operation
(SPDSEL is HIGH and BYTE8/10 is HIGH)
Min.
10
Max.
20
Unit
MHz
RXCLK Clock Output Frequency—50 to 100 MBaud 8-bit Operation
(SPDSEL is LOW and BYTE8/10 is HIGH)
5
10
MHz
RXCLK Clock Output Frequency—100 to 200 MBaud 10-bit Operation
(SPDSEL is HIGH and BYTE8/10 is LOW)
8.33
16.67 MHz
RXCLK Clock Output Frequency—50 to 100 MBaud 10-bit Operation
(SPDSEL is LOW and BYTE8/10 is LOW)
4.16
8.33
MHz
t_RXCLKOP
RXCLK Output Period
25
240
ns
t_RXCLKOD
t_RXCLKOR[16]
t_RXCLKOF[16]
RXCLK Output Duty Cycle
RXCLK Output Rise Time^[18]
RXCLK Output Fall Time^[18]
40
60
%
0.25
2
ns
0.25
2
ns
t_RXENS
Receive Enable Set-up Time to RXCLK↑
4
ns
Note:
19. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
20. The period of t_ROS will match the period of the transmitter PLL reference (REFCLK) when receiving serial data. When data is interrupted, RXCLK may drift to REFCLK +0.2%.
Document #: 38-02020 Rev. *C
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