CY7C9689A Datasheet, PDF (19/46 Pages) Cypress Semiconductor – TAXI-compatible HOTLink Transceiver

CY7C9689A
In discard policy 1, the JK or LM SYNC character, which is
automatically transmitted when no data is present in the
Transmit FIFO, is treated differently here. In this mode,
whenever two or more adjacent JK or LM characters are
received, all of them are discarded except the last one
received before any other character type. This allows these fill
characters to be removed from the data stream, but the last
SYNC character which can be used as a delimiter.
Policy 2 is identical to policy 1 except that all C5.0 characters
are removed from the data stream.
When the FIFOs are bypassed (FIFOBYP LOW), no
characters are actually discarded, but the receiver discard
policy can be used to control external filtering of the data. The
RXEMPTY FIFO flag is used to indicate if the character on the
output bus is valid or not. In discard policy 0, the RXEMPTY
flag is always deasserted to indicate that valid data is always
present. In discard policy 1, the RXEMPTY flag indicates an
empty condition for all but the last JK or LM character before
any other character is presented. In discard policy 2, the
RXEMPTY flag indicates an empty condition for all JK or LM
SYNC characters. When any other character is present, this
flag indicates that valid or “interesting” Data or Special
Characters are present.
Receive FIFO
The Receive FIFO is used to buffer data captured from the
selected serial stream for later processing by the host system.
This FIFO is sized to hold 256 14-bit characters. When the
FIFO is enabled, it is written to by the Receive Control State
Machine. When data is present in the Receive FIFO (as
indicated by the RXFULL, RXHALF, and RXEMPTY Receive
FIFO status flags), it can be read from the Output Register by
asserting CE and RXEN.
The read port on the Receive FIFO may be configured for the
same two timing models as the transmit interface: UTOPIA
and Cascade. Both are forms of a FIFO interface. The UTOPIA
timing model has active LOW RXEMPTY and RXFULL status
flags, and an active LOW RXEN enable. When configured for
Cascade operation, these same signals are all active HIGH.
Either timing model supports connection to various host bus
interfaces, state machines, or external FIFOs for depth
expansion (see Figure 4).
The Receive FIFO presents Full, Half-Full, and Empty FIFO
status flags. These flags are provided synchronous to RXCLK
to allow operation with a Moore-type external controlling state
machine. When configured with the Receive FIFO enabled,
RXCLK is an input. When the Receive FIFO is bypassed
(FIFOBYP is LOW), RXCLK is an output operating at the
received character rate.
EF*
REN*
Q
CY7C42x5 FIFO
EF*
FF*
REN* WEN*
Q
D
RXCLK _{RCLK WCLK}
CY7C9689A
RXEN
RXEMPTY
RXDATA
RXSC/D
RXCLK
“1” _EXTFIFO
Figure 4. External FIFO Depth Expansion of the
CY7C9689A Receive Data Path
Receive Input Register
The input register is clocked by the rising edge of RXCLK. It
samples numerous signals that control the reading of the
Receive FIFO and operation of the Receive Control State
Machine.
Receive Output Register
The Receive Output Register changes in response to the
rising edge of RXCLK. The Receive FIFO status flag outputs
of this register are placed in a High-Z state when the
CY7C9689A is not addressed (CE is sampled HIGH). The
RXDATA bus output drivers are enabled when the device is
selected by RXEN being asserted in the RXCLK cycle immedi-
ately following that in which the device was addressed (CE is
sampled LOW), and RXEN being sampled by RXCLK. This
initiates a Receive FIFO read cycle.
Just as with the TXDATA bus on the Transmit Input Register,
the receive outputs are also mapped by the specific decoding
and bus-width selected by the ENCBYP, BYTE8/10 and
FIFOBYP inputs. These assignments are shown in Table 6.
If the Receive FIFO and Decoder are bypassed, all received
characters are passed directly to the Receive Output Register.
If framing is enabled, and JK or LM sync characters have been
detected meeting the present framing requirements, the
output characters will appear on proper character boundaries.
If framing is disabled (RFEN is LOW) or sync characters have
not been detected in the data stream, the received characters
may not be output on their proper 10-bit boundaries. In this
mode, some form of external framing and decoding/descram-
bling must be used to recover the original source data.
Document #: 38-02020 Rev. *C
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