CY14C256Q_12 Datasheet, PDF (23/32 Pages) Cypress Semiconductor – 256-Kbit (32 K × 8) SPI nvSRAM

CY14C256Q
CY14B256Q
CY14E256Q
AC Switching Characteristics
Over the Operating Range^[10]
Cypress
Alt.
Parameter Parameter
Description
f_SCK
t_CL[11]
t_CH[11]
t_CS
t_CSS
t_CSH
t_SD
t_HD
t_HH
t_SH
t_CO
t_HHZ[11]
t_HLZ[11]
t_OH
t_HZCS[11]
f_SCK
t_WL
t_WH
t_CE
t_CES
t_CEH
t_SU
t_H
t_HD
t_CD
t_V
t_HZ
t_LZ
t_HO
t_DIS
Clock frequency, SCK
Clock pulse width LOW
Clock pulse width HIGH
CS HIGH time
CS setup time
CS hold time
Data in setup time
Data in hold time
HOLD hold time
HOLD setup time
Output Valid
HOLD to output HIGH Z
HOLD to output LOW Z
Output hold time
Output disable time
40 MHz
Min
Max
–
40
11
–
11
–
20
–
10
–
10
–
5
–
5
–
5
–
5
–
–
9
–
15
–
15
0
–
–
20
Figure 29. Synchronous Data Timing (Mode 0)
CS
SCK
SI
tCSS
tCH
tSD tHD
VALID IN
HI-Z
SO
CS
tCL
VALID IN
VALID IN
tCO
Figure 30. HOLD Timing
104 MHz
Min
Max
–
104
4.5
–
4.5
–
20
–
5
–
5
–
4
–
3
–
3
–
3
–
–
8
–
8
–
8
0
–
–
8
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCS
tCSH
tOH
tHZCS
HI-Z
SCK
HOLD
tHH
tSH
tHHZ
tHH
tSH
tHLZ
SO
Notes
10.
Test conditions assume signal transition time of 3 ns
I_OL/I_OH and load capacitance shown in Figure 28.
or
less,
timing
reference
levels
of
V_CC/2,
input
pulse
levels
of
0
to
V_CC
(typ),
and
output
loading
of
the
specified
11. These parameters are guaranteed by design and are not tested.
Document Number: 001-65282 Rev. *E
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