CY14C256Q_12 Datasheet, PDF (13/32 Pages) Cypress Semiconductor – 256-Kbit (32 K × 8) SPI nvSRAM

CY14C256Q
CY14B256Q
CY14E256Q
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Read Sequence (READ) Instruction
The read operations on this device are performed by giving the
instruction on the SI pin and reading the output on SO pin. The
following sequence needs to be followed for a read operation:
After the CS line is pulled LOW to select a device, the read
opcode is transmitted through the SI line followed by two bytes
of address. The MSB bit (A15) of the address is a “don’t care”.
After the last address bit is transmitted on the SI pin, the data
(D7-D0) at the specific address is shifted out on the SO line on
the falling edge of SCK starting with D7. Any other data on SI line
after the last address bit is ignored.
CY14X256Q allows reads to be performed in bursts through SPI
which can be used to read consecutive addresses without
issuing a new READ instruction. If only one byte is to be read,
the CS line must be driven HIGH after one byte of data comes
out. However, the read sequence may be continued by holding
the CS line LOW and the address is automatically incremented
and data continues to shift out on SO pin. When the last data
memory address (0x7FFF) is reached, the address rolls over to
0x0000 and the device continues to read.
Note The READ instruction operates up to a maximum of
40 MHz SPI frequency.
Fast Read Sequence (FAST_READ) Instruction
The FAST_READ instruction allows you to read memory at SPI
frequency above 40 MHz and up to 104 MHz (Max). The host
system must first select the device by driving CS low, the
FAST_READ instruction is then written to SI, followed by 2
address byte and then a dummy byte. The MSB bit (A15) of the
address is a “don’t care”.
From the subsequent falling edge of the SCK, the data of the
specific address is shifted out serially on the SO line starting with
MSB. The first byte specified can be at any location. The device
automatically increments to the next higher address after each
byte of data is output. The entire memory array can therefore be
read with a single FAST_READ instruction. When the highest
address in the memory array is reached, address counter rolls
over to start address 0x0000 and thus allowing the read
sequence to continue indefinitely. The FAST_READ instruction
is terminated by driving CS High at any time during data output.
Note FAST_READ instruction operates up to maximum of
104 MHz SPI frequency.
Write Sequence (WRITE) Instruction
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is write disabled,
then the device must first be write enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by two bytes of address and the data (D7-D0) which is
to be written. The MSB bit (A15) of the address is a “don’t care”.
CY14X256Q enables writes to be performed in bursts through
SPI which can be used to write consecutive addresses without
issuing a new WRITE instruction. If only one byte is to be written,
the CS line must be driven HIGH after the D0 (LSB of data) is
transmitted. However, if more bytes are to be written, CS line
must be held LOW and address is incremented automatically.
The following bytes on the SI line are treated as data bytes and
written in the successive addresses. When the last data memory
address (0x7FFF) is reached, the address rolls over to 0x0000
and the device continues to write. The WEN bit is reset to ‘0’ on
completion of a WRITE sequence.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
CS
SCK
SI
SO
Figure 12. Read Instruction Timing
0 1 2 34 5 67 0 1 23 45 6 7
12 13 14 15 0 1 2 3 4 5 6 7
Op-Code
15-bit Address
0 0 0 0 0 0 1 1 X A14 A13 A12 A11 A10 A9 A8
MSB
A3 A2 A1 A0
LSB
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Document Number: 001-65282 Rev. *E
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