CY8C27243_06 Datasheet, PDF (22/34 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C27x43 Automotive Data Sheet
3. Electrical Specifications
3.4 AC Electrical Characteristics
3.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-13: AC Chip-Level Specifications
Symbol
F_IMO24
F_CPU1
F_48M
F_24M
F_32K1
F_32K2
F_PLL
Jitter24M2
T_PLLSLEW
T_PLLSLEWS-
LOW
T_OS
T_OSACC
Jitter32k
T_XRST
DC24M
Step24M
Jitter24M1P
Jitter24M1R
F_MAX
T_RAMP
Description
Internal Main Oscillator Frequency for 24 MHz
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
PLL Frequency
24 MHz Period Jitter (PLL)
PLL Lock Time
PLL Lock Time for Low Gain Setting
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 200 ppm
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
24 MHz Period Jitter (IMO) Peak-to-Peak
24 MHz Period Jitter (IMO) Root Mean Squared
Maximum frequency of signal on row input or row output.
Supply Ramp Time
Min
22.95
0.90
–
0
15
–
–
–
0.5
0.5
–
–
–
10
40
–
–
–
–
0
Typ
24
12
–
24
32
32.768
23.986
–
–
–
1700
2800
100
–
50
50
300
–
–
–
Max
24.96
12.48
–
24.96^a
64
–
–
800
10
50
2620
3800
–
60
–
600
12.48
–
a. See the individual user module data sheets for information on maximum frequencies for user modules.
Units
MHz
MHz
MHz
MHz
kHz
kHz
MHz
ps
ms
ms
Notes
Trimmed. Utilizing factory trim values.
Not allowed.
Accuracy is capacitor and crystal dependent.
Is a multiple (x732) of crystal frequency.
ms
ms
ns
µs
%
kHz
ps
ps
MHz
µs
PLL
Enable
F_PLL
T_PLLSLEW
PLL
Gain ⁰
Figure 3-2. PLL Lock Timing Diagram
24 MHz
November 9, 2006
Document No. 38-12023 Rev. *D
22
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