CY7C1522V18 Datasheet, PDF (22/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

CY7C1522V18
CY7C1529V18
CY7C1523V18
CY7C1524V18
Switching Characteristics Over the Operating Range ^{[23, 24]}
Cypress Consortium
Parameter Parameter
Description
300 MHz 278 MHz 250 MHz 200 MHz 167 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t_POWER
VAc_DcDe(Tsysp[2i₅c_]al) to the first
1
1
1
1
1
ms
t_CYC
t_KHKH
K Clock and C Clock
Cycle Time
3.30 5.25 3.60 5.25 4.0 6.3 5.0 7.9 6.0 8.4 ns
t_KH
t_KHKL
Input Clock
1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns
(K/K and C/C) HIGH
t_KL
t_KLKH
Input Clock
1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns
(K/K and C/C) LOW
t_KHKH
t_KHKH
K Clock Rise to K Clock ^{1.49 – 1.6 – 1.8 – 2.2 – 2.7 – ns}
Rise and C to C Rise
(rising edge to rising
edge)
t_KHCH
t_KHCH
K/K Clock Rise to C/C ^{0.0 1.45 0.0 1.55 0.0 1.8 0.0 2.2 0.0 2.7 ns}
Clock Rise (rising edge to
rising edge)
Set-up Times
t_SA
t_AVKH
Address Set-up to K
0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
Clock Rise
t_SC
t_IVKH
Control Set-up to Clock 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
(K, K) Rise (LD, R/W)
t_SCDDR
t_IVKH
t_SD[26]
t_DVKH
Double Data Rate
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Control Set-up to Clock
(K, K) Rise (BWS₀,
BWS_1, BWS₂, BWS₃)
D_[X:0] Set-up to Clock
(K and K) Rise
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Hold Times
t_HA
t_KHAX
Address Hold after Clock 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
(K and K) Rise
t_HC
t_KHIX
Control Hold after Clock 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
(K and K) Rise (LD, R/W)
t_HCDDR
t_KHIX
t_HD
t_KHDX
Double Data Rate
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Control Hold after Clock
(K and K) Rise (BWS₀,
BWS_1, BWS₂, BWS₃)
D_[X:0] Hold after Clock 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
(K and K) Rise
Output Times
t_CO
t_CHQV
C/C Clock Rise
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
(or K/K in single clock
mode) to Data Valid
t_DOH
t_CHQX
Data Output Hold after –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
Output C/C Clock Rise
(Active to Active)
Notes:
24. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
25. This part has a voltage regulator internally; t_POWER is the time that the power needs to be supplied above V_DD minimum initially before a read or write operation
can be initiated.
26. For D0 data signal on CY7C1529V18 device, t_SD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
Document #: 38-05564 Rev. *D
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