CY14B104K_12 Datasheet, PDF (22/34 Pages) Cypress Semiconductor – 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock

CY14B104K, CY14B104M
Software Controlled STORE and RECALL Cycle
Over the Operating Range
Parameter ^{[47, 48]}
Description
t_RC
t_SA
t_CW
t_HA
t_RECALL
t_SS ^{[49, 50]}
STORE/RECALL initiation cycle time
Address setup time
Clock pulse width
Address hold time
RECALL duration
Soft sequence processing time
25 ns
Min
Max
25
–
0
–
20
–
0
–
–
200
–
100
45 ns
Min
Max
Unit
45
–
ns
0
–
ns
30
–
ns
0
–
ns
–
200
s
–
100
s
Switching Waveforms – Software Controlled STORE/RECALL Cycle
Figure 13. CE and OE Controlled Software STORE and RECALL Cycle ^[48]
t_RC
t_RC
Address
Address #1
t_SA
t_CW
Address #6
t_CW
CE
t_SA
OE
t_HA
t_HA
t_HA
t_HA
HSB (STORE only)
DQ (DATA)
t_LZCE
t_HZCE
t _DELAY
51
Note
High Impedance
t_STORE/t_RECALL
t_HHHD
t_LZHSB
RWI
Address
Figure 14. Autostore Enable and Disable Cycle ^[48]
t_RC
t_RC
Address #1
t_SA
t_CW
Address #6
t_CW
CE
t_SA
OE
DQ (DATA)
t_LZCE
t_HA
t_HA
t_HZCE
t_HA
t_HA
51
Note
t_SS
t _DELAY
RWI
Notes
47. The software sequence is clocked with CE controlled or OE controlled reads.
48. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.
49. This is the amount of time it takes to take action on a soft sequence command. V_CC power must remain HIGH to effectively register command.
50. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
51. DQ output data at the sixth read may be invalid since the output is disabled at t_DELAY time.
Document Number: 001-07103 Rev. *Z
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