CY14B104K_12 Datasheet, PDF (13/34 Pages) Cypress Semiconductor – 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock

CY14B104K, CY14B104M
Table 4. Register Map Detail (continued)
Register
CY14B104K CY14B104M
0x7FFF8
0x3FFF8
OSCEN
Calibration Sign
Calibration
0x7FFF7
0x3FFF7
WDS
WDW
Description
Calibration/Control
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
0
Calibration
sign
Calibration
Oscillator enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs.
Disabling the oscillator saves battery or capacitor power during storage.
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from
the time-base.
These five bits control the calibration of the clock.
WatchDog Timer
D7
D6
D5
D4
D3
D2
D1
D0
WDS
WDW
WDT
Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to
‘0’ has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit
is write only. Reading it always returns a ‘0’.
Watchdog write enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value
(D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value.
Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write
cycle is complete. This function is explained in more detail in Watchdog Timer on page 8.
WDT
0x7FFF6
0x3FFF6
WIE
AIE
PFE
0
H/L
P/L
0x7FFF5
0x3FFF5
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is
31.25 ms (a setting of ‘1’) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to ‘0’
disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.
Interrupt Status/Control
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
0
H/L
P/L
0
0
Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer
drives the INT pin and the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF
flag.
Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When
set to ‘0’, the alarm match only affects the AF flag.
Power fail enable. When set to ‘1’, the power fail monitor drives the INT pin and the PF flag. When
set to ‘0’, the power fail monitor affects only the PF flag.
Reserved for future use
High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0,’ the INT pin is open
drain, active LOW.
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L)
until the flags register is read.
Alarm - Day
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s alarm date
Alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date
value.
M
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the date value.
Document Number: 001-07103 Rev. *Z
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