CY8CPLC20_11 Datasheet, PDF (21/56 Pages) Cypress Semiconductor – Powerline Communication Solution Frequency shift keying modulation

CY8CPLC20
Table 8-2. Register Map Bank 1 Table: Configuration Space
Name
Addr (1,Hex) Access
Name Addr (1,Hex) Access
PRT0DM0 00
RW
DBB20FN 40
RW
PRT0DM1 01
RW
DBB20IN 41
RW
PRT0IC0
02
RW
DBB20OU 42
RW
PRT0IC1
03
RW
43
PRT1DM0 04
RW
DBB21FN 44
RW
PRT1DM1 05
RW
DBB21IN 45
RW
PRT1IC0
06
RW
DBB21OU 46
RW
PRT1IC1
07
RW
47
PRT2DM0 08
RW
DCB22FN 48
RW
PRT2DM1 09
RW
DCB22IN 49
RW
PRT2IC0
0A
RW
DCB22OU 4A
RW
PRT2IC1
0B
RW
4B
PRT3DM0 0C
RW
DCB23FN 4C
RW
PRT3DM1 0D
RW
DCB23IN 4D
RW
PRT3IC0
0E
RW
DCB23OU 4E
RW
PRT3IC1
0F
RW
4F
PRT4DM0 10
RW
DBB30FN 50
RW
PRT4DM1 11
RW
DBB30IN 51
RW
PRT4IC0
12
RW
DBB30OU 52
RW
PRT4IC1
13
RW
53
PRT5DM0 14
RW
DBB31FN 54
RW
PRT5DM1 15
RW
DBB31IN 55
RW
PRT5IC0
16
RW
DBB31OU 56
RW
PRT5IC1
17
RW
57
PRT6DM0 18
RW
DCB32FN 58
RW
PRT6DM1 19
RW
DCB32IN 59
RW
PRT6IC0
1A
RW
DCB32OU 5A
RW
PRT6IC1
1B
RW
5B
PRT7DM0 1C
RW
DCB33FN 5C
RW
PRT7DM1 1D
RW
DCB33IN 5D
RW
PRT7IC0
1E
RW
DCB33OU 5E
RW
PRT7IC1
1F
RW
5F
DBB00FN 20
RW
CLK_CR0 60
RW
DBB00IN
21
RW
CLK_CR1 61
RW
DBB00OU 22
RW
ABF_CR0 62
RW
23
AMD_CR0 63
RW
DBB01FN 24
RW
64
DBB01IN
25
RW
65
DBB01OU 26
RW
AMD_CR1 66
RW
27
ALT_CR0 67
RW
DCB02FN 28
RW
ALT_CR1 68
RW
DCB02IN
29
RW
CLK_CR2 69
RW
DCB02OU 2A
RW
6A
2B
6B
DCB03FN 2C
RW
TMP_DR0 6C
RW
DCB03IN
2D
RW
TMP_DR1 6D
RW
DCB03OU 2E
RW
TMP_DR2 6E
RW
2F
TMP_DR3 6F
RW
DBB10FN 30
RW
ACB00CR3 70
RW
DBB10IN
31
RW
ACB00CR0 71
RW
DBB10OU 32
RW
ACB00CR1 72
RW
33
ACB00CR2 73
RW
DBB11FN
34
RW
ACB01CR3 74
RW
DBB11IN
35
RW
ACB01CR0 75
RW
DBB11OU 36
RW
ACB01CR1 76
RW
37
ACB01CR2 77
RW
DCB12FN 38
RW
ACB02CR3 78
RW
DCB12IN
39
RW
ACB02CR0 79
RW
DCB12OU 3A
RW
ACB02CR1 7A
RW
3B
ACB02CR2 7B
RW
DCB13FN 3C
RW
ACB03CR3 7C
RW
DCB13IN
3D
RW
ACB03CR0 7D
RW
DCB13OU 3E
RW
ACB03CR1 7E
RW
3F
ACB03CR2 7F
RW
Blank fields are Reserved and should not be accessed.
Name Addr (1,Hex)
ASC10CR0 80
ASC10CR1 81
ASC10CR2 82
ASC10CR3 83
ASD11CR0 84
ASD11CR1 85
ASD11CR2 86
ASD11CR3 87
ASC12CR0 88
ASC12CR1 89
ASC12CR2 8A
ASC12CR3 8B
ASD13CR0 8C
ASD13CR1 8D
ASD13CR2 8E
ASD13CR3 8F
ASD20CR0 90
ASD20CR1 91
ASD20CR2 92
ASD20CR3 93
ASC21CR0 94
ASC21CR1 95
ASC21CR2 96
ASC21CR3 97
ASD22CR0 98
ASD22CR1 99
ASD22CR2 9A
ASD22CR3 9B
ASC23CR0 9C
ASC23CR1 9D
ASC23CR2 9E
ASC23CR3 9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
DEC_CR2
IMO_TR
ILO_TR
BDG_TR
ECO_TR
CPU_F
FLS_PR1
CPU_SCR1
CPU_SCR0
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
W
W
RW
W
RL
RW
#
#
Document Number: 001-48325 Rev. *J
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