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CY8C24633-24PVXIT Datasheet, PDF (21/52 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip | |||
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CY8C24633
DC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and â40 °C ï£ TA ï£ 85 °C, or 3.0 V to 3.6 V and â40 °C ï£ TA ï£ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 13. 5 V DC Analog Output Buffer Specifications
Symbol
Description
CL
Load capacitance
VOSOB
TCVOSOB
VCMOB
ROUTOB
Input offset voltage (absolute value)
Average input offset voltage drift
Common-mode input voltage range
Output resistance
Power = low
Power = high
VOHIGHOB High output voltage swing
(Load = 32ï to Vdd/2)
Power = low
Power = high
VOLOWOB Low output voltage swing
(Load = 32ï to Vdd/2)
Power = low
Power = high
ISOB
Supply current including bias cell
(no load)
Power = low
Power = high
PSRROB Supply voltage rejection ratio
Min
Typ
Max
Units
Notes
â
â
200
pF This specification applies to
the external circuit that is
being driven by the analog
output buffer.
â
3
12
mV
â
+6
â
ïV/°C
0.5
â
Vdd - 1.0
V
â
1
â
W
â
1
â
W
0.5 x Vdd + 1.1 â
â
V
0.5 x Vdd + 1.1 â
â
V
â
â 0.5 x Vdd - 1.3 V
â
â 0.5 x Vdd - 1.3 V
â
1.1
5.1
mA
â
2.6
8.8
mA
52
64
â
dB VOUT > (Vdd - 1.25).
Table 14. 3.3 V DC Analog Output Buffer Specifications
Symbol
Description
CL
Load capacitance
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Input offset voltage (absolute value)
average input offset voltage drift
Common-mode input voltage range
Output resistance
Power = low
Power = high
High output voltage swing
(Load = 1 kï to Vdd/2)
Power = low
Power = high
Low output voltage swing
(Load = 1 kï to Vdd/2)
Power = low
Power = high
Supply current including bias cell
(No Load)
Power = low
Power = high
Supply voltage rejection ratio
Min
Typ
Max
Units
Notes
â
â
200
pF This specification applies to
the external circuit that is
being driven by the analog
output buffer.
â
3
12
mV
â
+6
â
ïV/°C
0.5
â
Vdd â 1.0
V
â
1
â
W
â
1
â
W
0.5 x Vdd + 1.0 â
â
V
0.5 x Vdd + 1.0 â
â
V
â
â 0.5 x Vdd - 1.0 V
â
â 0.5 x Vdd - 1.0 V
â
0.8
2.0
mA
â
2.0
4.3
mA
52
64
â
dB VOUT > (Vdd - 1.25).
Document Number: 001-20160 Rev. *H
Page 21 of 52
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