CY7C1371D_12 Datasheet, PDF (21/37 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture

Boundary Scan Order
119-ball BGA ^{[15, 16]}
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Ball ID
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
H6
G7
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M4
A5
K4
E4
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
G1
H2
D1
E2
G2
H1
J3
2K
CY7C1371D
CY7C1373D
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
M2
N1
P1
K1
L2
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
Internal
Notes
15. Balls which are NC (No Connect) are pre-set LOW.
16. Bit# 85 is pre-set HIGH.
Document Number: 38-05556 Rev. *L
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