CY7C1371D_12 Datasheet, PDF (1/37 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture

CY7C1371D
CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through
SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture
Features
■ No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states
❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
■ 3.3 V/2.5 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 119-ball BGA, and 165-ball FBGA packages
■ Three chip enables for simple depth expansion
■ Automatic power-down feature available using ZZ mode or CE
deselect
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18
synchronous flow through burst SRAM designed specifically to
support unlimited true back-to-back read/write operations with
no wait state insertion. The CY7C1371D/CY7C1373D is
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BW_X) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz 100 MHz Unit
6.5
8.5
ns
210
175
mA
70
70
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05556 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 5, 2012