CY28324_02 Datasheet, PDF (21/23 Pages) Cypress Semiconductor – FTG for Intel® Pentium® 4 CPU and Chipsets

Layout Example
PRELIMINARY
CY28324
FB
0.005 µF
C4
G
VDDQ3
C3
G
G
G
G
VDDQ3
5Ω
1
2^V
3^G
4
G ⁴⁸
47
V ₄₆
G
G ₄₅
5^G
44
6
G ₄₃
7
42
8^G
41
9^V
G ₄₀
10 ^G
V ₃₉
G
11
G ₃₈
12
37
13 ^G
G ₃₆
14
35
15
V ₃₄
G
16
G 33
17 ^G
V ₃₂
G
18 ^V
31
19
30
20
G ₂₉
21 ^G
28
22
27
23
24* ^G
26
G ₂₅
C5 G G C6
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
Cermaic Caps C3 = 10–22 µF C4 = 0.005 µF C5 = 10 µF C6 = 0.1 µF
G = VIA to GND plane layer V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1 µF ceramic
* For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3
Document #: 38-07002 Rev. *B
Page 21 of 23