CY14MB064J1A_13 Datasheet, PDF (21/28 Pages) Cypress Semiconductor – 64-Kbit (8 K x 8) Serial (I2C) nvSRAM

CY14MB064J1A/CY14MB064J2A
CY14ME064J1A/CY14ME064J2A
AC Switching Characteristics
Over the Operating Range
Parameter
[10]
Description
f_SCL
t_{SU; STA}
t_HD;STA
t_LOW
t_HIGH
t_SU;DATA
t_HD;DATA
t_DH
t_r[12]
t_f[12]
t_SU;STO
t_VD;DATA
t_VD;ACK
t_OF[12]
t_BUF
t_SP
Clock frequency, SCL
Setup time for Repeated START
condition
Hold time for START condition
LOW period of the SCL
HIGH period of the SCL
Data in setup time
Data hold time (In/Out)
Data out hold time
Rise time of SDA and SCL
Fall time of SDA and SCL
Setup time for STOP condition
Data output valid time
ACK output valid time
Output fall time from V_IH(min) to
V_IL(max)
Bus free time between STOP and
next START condition
Pulse width of spikes that must be
suppressed by input filter
3.4 MHz ^[11]
Min
Max
–
3400
160
–
160
–
160
–
60
–
10
–
0
–
0
–
–
80
–
80
160
–
–
130
–
130
–
80
0.3
–
–
10
1 MHz ^[11]
Min
Max
–
1000
250
–
250
–
500
–
260
–
100
–
0
–
0
–
–
120
–
120
250
–
–
400
–
400
–
120
0.5
–
–
50
400 kHz ^[11]
Min
Max
–
400
600
–
Unit
kHz
ns
600
1300
600
100
0
0
–
–
600
–
–
–
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
300
ns
300
ns
–
ns
900
ns
900
ns
250
ns
1.3
–
us
–
50
ns
Switching Waveforms
Figure 30. Timing Diagram
SDA
SCL
t_r
t_LOW
t_HIGH
t_SU;DATA
t_HD;STA
S
START condition
t_HD;DATA
t_VD;DAT
t_f
t_HD;STA
t_SU;STA
Sr
t_f t_r
Repeated START condition
t_SP
t_VD;ACK t_SU;STO
t_BUF
9th clock
(ACK)
P
S
STOP condition START condition
Notes
10. Test conditions assume signal transition time of 10 ns or less, timing reference levels of V_CC/2, input pulse levels of 0 to V_CC(typ), and output loading of the specified
11.
I_OL and load capacitance shown in Figure 29.
Bus Load (Cb) considerations; Cb < 500 pF for
I²C
clock
frequency
(SCL)
100/400
KHz;
Cb
<
550
pF
for
SCL
at
1000
kHz;
Cb
<
100
pF
for
SCL
at
3.4
MHz.
12. These parameters are guaranteed by design and are not tested.
Document Number: 001-70393 Rev. *I
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