CY14MB064J1A_13 Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 64-Kbit (8 K x 8) Serial (I2C) nvSRAM

CY14MB064J1A/CY14MB064J2A
CY14ME064J1A/CY14ME064J2A
64-Kbit (8 K × 8) Serial (I²C) nvSRAM
64-Kbit (8 K × 8) Serial (I2C) nvSRAM
Features
■ 64-Kbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 8 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I²C
command (Software STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I²C command (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
(except for CY14MX064J1A)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 C
■ High speed I²C interface^[1]
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast-mode Plus: 1 MHz speed
❐ High speed: 3.4 MHz
❐ Zero cycle delay reads and writes
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for 1/4, 1/2, or entire array
■ I²C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8 byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■ Low power consumption
❐ Average active current of 1 mA at 3.4-MHz operation
❐ Average standby mode current of 120 µA
❐ Sleep mode current of 8 µA
■ Industry standard configurations
❐ Operating voltages:
• CY14MB064J: V_CC = 2.7 V to 3.6 V
• CY14ME064J: V_CC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14MX064J combines a 64-Kbit nvSRAM^[2] with
a nonvolatile element in each memory cell. The memory is
organized as 8 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14MX064J1A). On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
The STORE and RECALL operations can also be initiated by the
user through I²C commands.
Configuration
Feature
AutoStore
Software STORE
Slave Address pins
CY14MX064J1A
No
Yes
A2, A1, A0
CY14MX064J2A
Yes
Yes
A2, A1
Logic Block Diagram
VCC VCAP
SDA
SCL
A2, A1, A0
WP
Power Control
Block
Sleep
2
I C Control Logic
Slave Address
Decoder
Serial Number
8x8
Manufacturer ID /
Product ID
Memory Control Register
Command Register
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
Quantum Trap
8Kx8
SRAM
8Kx8
STORE
RECALL
Notes
1. The I²C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on
chips which support only one mode of operation. Refer to AN87209 for more details.
2. Serial (I²C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70393 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 3, 2013