CY7C1371DV33 Datasheet, PDF (20/29 Pages) Cypress Semiconductor – 18-Mbit (512 K x 36) Flow-Through SRAM with NoBL™ Architecture

Switching Characteristics
Over the Operating Range
Parameter ^{[17, 18]}
Description
t_POWER[19]
Clock
t_CYC
t_CH
t_CL
Output Times
t_CDV
t_DOH
t_CLZ
t_CHZ
t_OEV
t_OELZ
t_OEHZ
Setup Times
t_AS
t_ALS
t_WES
t_CENS
t_DS
t_CES
Hold Times
t_AH
t_ALH
t_WEH
t_CENH
t_DH
t_CEH
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z ^{[20, 21, 22]}
Clock to high Z ^{[20, 21, 22]}
OE LOW to output valid
OE LOW to output low Z ^{[20, 21, 22]}
OE HIGH to output high Z ^{[20, 21, 22]}
Address setup before CLK rise
ADV/LD setup before CLK rise
WE, BW_X setup before CLK rise
CEN setup before CLK rise
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BW_X hold after CLK rise
CEN hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
CY7C1371DV33
133 MHz
Unit
Min
Max
1
–
ms
7.5
–
ns
2.1
–
ns
2.1
–
ns
–
6.5
ns
2.0
–
ns
2.0
–
ns
–
4.0
ns
–
3.2
ns
0
–
ns
–
4.0
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
Notes
17. Timing reference level is 1.5 V when V_DDQ = 3.3 V and is 1.25 V when V_DDQ = 2.5 V.
18. Test conditions shown in (a) of Figure 4 on page 19 unless otherwise noted.
19.
This part has
be initiated.
a
voltage
regulator
internally;
t_POWER
is
the
time
that
the
power
needs
to
be
supplied
above
V_DD(minimum)
initially,
before
a
read
or
write
operation
can
20. t_CHZ, t_CLZ, t_OELZ, and t_OEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 19. Transition is measured ±200 mV from steady-state voltage.
21.
At any
These
svpoeltcaigfiecaatniodnstedmopneortaitmurpel,yta^OEb^Hu^Zs
icsolnetsesnttihoanncto_{OnEdLiZtioann,dbtuCtHreZfilseclet} spsartahmanette_{CrLsZgtuoaerlaimntieneadteobvuesr}
contention
worst case
between SRAMs when
user conditions. Device
sharing the
is designed
same data bus.
to achieve high Z
prior to low Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
Document Number: 001-75433 Rev. *A
Page 20 of 29