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| CY7C0851V Datasheet, PDF (20/39 Pages) Cypress Semiconductor – FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM | |||
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CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Switching Waveforms (continued)
Figure 10. Bank Select Read [33, 34]
CLK
tSA
ADDRESS(B1)
tSC
CE(B1)
DATAOUT(B1)
tSA
ADDRESS(B2)
CE(B2)
tSC
DATAOUT(B2)
tCYC2
tCH2
tCL2
tHA
A0
A1
A2
tHC
A3
A4
tHA
A0
tCD2
tSC tHC tCD2
Q0
tDC
A1
A2
tSC
tHC
tCKHZ
Q1
tDC
A3
tCD2
tCKLZ
A4
tHC
tCD2
tCKHZ
Q2
tCKLZ
Figure 11. Read-to-Write-to-Read (OE = LOW) [32, 35, 36, 37, 38]
CLK
tCYC2
tCH2
tCL2
A5
tCKHZ
Q3
A5
tCD2
Q4
tCKLZ
CE
tSC
tHC
R/W
tSW
tHW
An
ADDRESS
tSA
tHA
DATAIN
DATAOUT
tSW
tHW
An+1
tCD2
READ
An+2
tCKHZ
An+2
tSD tHD
Dn+2
An+3
tCD2
Qn
NO OPERATION
tCKLZ
WRITE
An+4
Qn+1
tCD2
Qn+3
READ
Notes
33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV
device from this data sheet. ADDRESS(B1) = ADDRESS(B2).
34. ADS = CNTEN= B0 â B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
36. During âNo Operation,â data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
37. CE0 = OE = B0 â B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
38. CE0 = B0 â B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document Number: 38-06070 Rev. *L
Page 20 of 39
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