CY7C0851V Datasheet, PDF (1/39 Pages) Cypress Semiconductor – FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM

CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36
Synchronous Dual-Port RAM
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM
Features
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ Synchronous pipelined operation
■ Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices
■ Pipelined output mode allows fast operation
■ 0.18-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed and power
■ High-speed clock to data access
■ 3.3 V low power
❐ Active as low as 225 mA (typ)
❐ Standby as low as 55 mA (typ)
■ Mailbox function for message passing
■ Global master reset
■ Separate byte enables on both ports
■ Commercial and industrial temperature ranges
■ IEEE 1149.1-compatible Joint test action group (JTAG)
boundary scan
■ 172-Ball fine-pitch ball grid array (FBGA) (1 mm pitch)
(15 mm × 15 mm)
■ 176-Pin thin quad plastic flatpack (TQFP)
(24 mm × 24 mm × 1.4 mm)
■ Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
■ Counter readback on address lines
■ Mask register readback on address lines
■ Dual chip enables on both ports for easy depth expansion
Functional Description
The FLEx36™ family includes 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE₀ or LOW on CE₁ for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853V/CY7C0853AV device in this family has limited
features. Please see Address Counter and Mask Register
Operations on page 9 for details.
Product Selection Guide
Density
2-Mbit (64 K × 36)
4-Mbit (128 K × 36)
Part number
CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV
Max. speed (MHz)
167
167
Max. access time - clock to data (ns)
4.0
4.0
Typical operating current (mA)
225
225
Package
176-pin TQFP, 172-ball FBGA 176-pin TQFP, 172-ball FBGA
9-Mbit (256 K × 36)
CY7C0853V/CY7C0853AV
133
4.7
270
172-ball FBGA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06070 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 7, 2012