ICD2051 Datasheet, PDF (2/8 Pages) Cypress Semiconductor – Dual Programmable Clock Generator

ICD2051:1/95
Revision: April 11, 1995
ICD2051
Pin Configuration
SCLKB
MUXREFB
OEB
GND
f_(REF)/XTALIN
XTALOUT
XBUF
CLKB
SOIC
Top View
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
DATA
MUXREFA
OE_A
V_DD
SCLKA
CLKA/4
CLKA/2
CLKA
ICD2051–2
Pin Summary
Name
SCLKB
MUXREFB
OEB
Number
1
2
3
Description
Serial clock input line for CLKB
MUXREFB = 0, CLKB equals input reference frequency
MUXREFB = 1, CLKB equals programmed frequency
This is used if glitch-free frequency changes are required.
Three-states CLKB outputs when pulled LOW. (Internal pull-up allows for no-connect if three-state
operation is not needed.)
GND
4
Xf^RT^EA^FL/ IN^[1]
5
XTALOUT^[1] 6
XBUF
7
CLKB
8
CLKA
9
CLKA/2
10
CLKA/4
11
Ground
Reference Oscillator input for all internal phase-locked loops
Oscillator output to a reference crystal.
Buffered Crystal Oscillator Output
CLKB Programmable Output
CLKA Programmable Output
CLKA divided by 2 (low skew)
CLKA divided by 4
SCLKA
12
V_DD
13
OEA
14
MUXREFA 15
Serial clock input line for CLKA.
+5V
Three-states CLKA outputs when pulled LOW. (Internal pull-up allows for no-connect if three-state
operation is not needed.)
MUXREFA = 0, CLKA equals input reference frequency
MUXREFA = 1, CLKA equals programmed frequency
This is used if glitch-free frequency changes are required.
DATA
16
Serial data input line for both programmable PLLs
Note:
1. For best accuracy, use a parallel-resonant crystal, assume C_LOAD = 17 pF.
2