CYDM064B16_08 Datasheet, PDF (2/24 Pages) Cypress Semiconductor – 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL® Dual-Port Static RAM

CYDM064B16, CYDM128B16, CYDM256B16
Logic Block Diagram ^{[1, 2]}
IO[15:0]_L
UB_L
LB_L
IO
Control
IO
Control
IO[15:0]_R
UB_R
LB_R
16K X 16
Dual Ported Array
A[13:0]_L
CE _L
OE _L
R/W _L
SEM_L
BUSY _L
INT_L
IRR₀ ,IRR₁
Address Decode
Address Decode
Mailboxes
CE_L
OE_L
R/W_L
Interrupt
Arbitration
Semaphore
M/S
INT_R
Input Read
Register and
Output Drive
Register
SFEN
CE _R
OE _R
R/W _R
ODR₀ - ODR₄
A [13:0]_R
CE _R
OE _R
R/W _R
SEM_R
BUSY _R
Notes
1. A₀–A₁₁ for 4K devices; A₀–A₁₂ for 8K devices; A₀–A₁₃ for 16K devices.
2. BUSY is an output in master mode and an input in slave mode.
Document #: 001-00217 Rev. *F
Page 2 of 24
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