CY7C1352G_12 Datasheet, PDF (2/20 Pages) Cypress Semiconductor – 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture

CY7C1352G
Logic Block Diagram – CY7C1352G
A0, A1, A
MODE
CLK
C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
O
U
T
S
E
N
P
U
T
O
U
T
D
P
A
U
T
T
WRITE
DRIVERS
S
MEMORY E
ARRAY
A
M
P
S
R
E
G
I
S
T
E
R
S
A
B
S
U
T
F
E
F
E
E
R
R
I
S
N
G
DQs
DQPA
DQPB
E
E
INPUT
REGISTER 1 E
INPUT
REGISTER0 E
OE
CE1
READ LOGIC
CE2
CE3
ZZ
Sleep
Control
Document Number: 38-05514 Rev. *J
Page 2 of 20