CY7C1352G_12 Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture

CY7C1352G
4-Mbit (256 K × 18) Pipelined SRAM with
NoBL™ Architecture
4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Byte write capability
■ 256 K × 18 common I/O architecture
■ 3.3 V core power supply (V_DD)
■ 2.5 V/3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 4.0 ns (for 133-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable (OE)
■ Available in Pb-free 100-pin TQFP package
■ Burst capability – linear or interleaved burst order
■ ZZ sleep mode option and stop clock option
Functional Description
The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1352G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 4.0 ns
(133-MHz device).
Write operations are controlled by the two byte write select
(BW_[A:B]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz Unit
4.0
ns
225
mA
40
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05514 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 21, 2012