CY62157EV30_09 Datasheet, PDF (2/15 Pages) Cypress Semiconductor – 8 Mbit (512K x 16) Static RAM

CY62157EV30 MoBL^®
Pin Configuration
Figure 1. 48-Ball VFBGA (Top View) ^[2]
12 345 6
BLE OE A₀ A₁ ^A2 ^CE2 A
IO₈ BHE A₃ A₄ CE₁ IO₀
B
IO₉ IO₁₀ A₅ A₆ IO₁ IO₂
C
V_SS IO₁₁ A₁₇ A₇ IO₃ VCC
D
V_CC IO₁₂ NC A₁₆ IO₄ V_SS
E
IO₁₄ IO₁₃ A₁₄ A₁₅ IO₅ IO₆
F
IO₁₅ NC A₁₂ A₁₃ WE IO₇
G
A₁₈ A₈ A₉ A₁₀ A₁₁ NC
H
Figure 2. 44-Pin TSOP II (Top View) ^[3]
A_{4 1}
A₃ 2
A₂ 3
A₁ 4
A₀ 5
CE 6
IO₀ 7
IO₁ 8
IO₂ 9
IO₃ 10
V_CC 11
V_{SS 12}
IO_{4 13}
IO_{5 14}
IO_{6 15}
IO_{7 16}
WE 17
A_{18 18}
A_{17 19}
A_{16 20}
A_{15 21}
A₁₄ 22
44 ^A5
43 ^A6
42 ^A7
41 OE
40 BHE
39 BLE
38 IO₁₅
37 IO₁₄
36 IO₁₃
35 IO₁₂
34 V_SS
33 V_CC
32 IO₁₁
31 IO₁₀
30 IO₉
29 IO₈
28 _A8
27 A₉
26 A₁₀
25 A₁₁
24 A₁₂
23 A₁₃
Figure 3. 48-Pin TSOP I (512K x 16/1M x 8) (Top View) ^{[2, 4]}
Product Portfolio
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
NC 9
DNU 10
WE 11
CE2 12
DNU 13
BHE 14
BLE 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
48 A16
47 BYTE
46 Vss
45 IO15/A19
44 IO7
43 IO14
42 IO6
41 IO13
40 IO5
39 IO12
38 IO4
37 Vcc
36 IO11
35 IO3
34 IO10
33 IO2
32 IO9
31 IO1
30 IO8
29 IO0
28 OE
27 Vss
26 CE1
25 A0
Product
Range
CY62157EV30LL
Ind’l/Auto-A
Auto-E
V_CC Range (V)
Min Typ ^[1] Max
2.2
3.0
3.6
2.2
3.0
3.6
Speed
(ns)
Power Dissipation
Operating I_CC, (mA)
f = 1 MHz
f = f_max
Typ ^[1] Max Typ ^[1] Max
Standby, I_SB2
(μA)
Typ ^[1] Max
45
1.8
3
18
25
2
8
55
1.8
4
18
35
2
30
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V_CC = V_CC(typ), T_A = 25°C.
2. NC pins are not connected on the die.
3. The 44-TSOP II package has only one chip enable (CE) pin.
4. The BYTE pin in the 48-TSOP I package must be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and IO8 to IO14 pins are not used (DNU).
Document #: 38-05445 Rev. *F
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