CY62157EV30_09 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 8 Mbit (512K x 16) Static RAM

CY62157EV30 MoBL^®
8 Mbit (512K x 16) Static RAM
Features
■ TSOP I Package Configurable as 512K x 16 or 1M x 8 SRAM
■ High Speed: 45 ns
■ Temperature Ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Wide Voltage Range: 2.20V to 3.60V
■ Pin Compatible with CY62157DV30
■ Ultra Low Standby Power
❐ Typical standby current: 2 μA
❐ Maximum standby current: 8 μA (Industrial)
■ Ultra Low Active Power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Easy Memory Expansion with CE₁, CE₂, and OE Features
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Available in Pb-free and non Pb-free 48-Ball VFBGA, Pb-free
44-Pin TSOP II and 48-Pin TSOP I Packages
Functional Description
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE₁ HIGH or CE₂ LOW or
both BHE and BLE are HIGH). The input or output pins (IO₀
through IO₁₅) are placed in a high impedance state when the
device is deselected (CE₁HIGH or CE₂ LOW), the outputs are
disabled (OE HIGH), Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is active (CE₁
LOW, CE₂ HIGH and WE LOW).
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO₀ through IO₇) is written
into the location specified on the address pins (A₀ through A₁₈).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO₈
through IO₁₅) is written into the location specified on the address
pins (A₀ through A₁₈).
To read from the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO₀ to IO₇. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO₈ to IO₁₅. See the Truth Table on page 10
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
512K × 16/1M x 8
A₅
RAM Array
A₄
A₃
A₂
A₁
A₀
IO₀–IO₇
IO₈–IO₁₅
Power Down
Circuit
COLUMN DECODER
CE₂
CE₁
BHE
BLE
BYTE
BHE
WE
OE
BLE
CE₂
CE₁
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05445 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 26, 2009
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