CY2XP21ZXC Datasheet, PDF (2/7 Pages) Cypress Semiconductor – 125 MHz LVPECL Clock Generator

PRELIMINARY
CY2XP21
Frequency Table
Crystal Frequency (MHz)
25
26.6
Inputs
PLL Multiplier Value
5
5
Output Frequency (MHz)
125
133
Absolute Maximum Conditions
Parameter
Description
V_DD
V_IN[1]
T_S
T_J
ESD_HBM
UL–94
Θ_JA[2]
Supply Voltage
Input Voltage, DC
Temperature, Storage
Temperature, Junction
ESD Protection, Human Body Model
Flammability Rating
Thermal Resistance, Junction to Ambient
Conditions
Relative to V_SS
Non operating
JEDEC STD 22-A114-B
At 1/8 in.
0 m/s airflow
1 m/s airflow
2.5 m/s airflow
Min
Max
–0.5
4.4
–0.5
–65
V_DD + 0.5
150
135
2000
V–0
100
91
87
Unit
V
V
°C
°C
V
°C/W
Operating Conditions
Parameter
Description
Min
Max
Unit
V_DD
3.3V Supply Voltage
2.5V Supply Voltage
3.135
3.465
V
2.375
2.625
V
T_A
Ambient Temperature, Commercial
Ambient Temperature, Industrial
0
70
°C
–40
85
°C
T_PU
Power up time for all V_DD to reach minimum specified voltage (ensure power ramps 0.05
500
ms
is monotonic)
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
I_DD[4]
V_OH
V_OL
V_OD1
V_OD2
V_OCM
Operating Supply Current with V_DD = 3.465V, Output terminated
–
output terminated
V_DD = 2.625V, Output terminated
–
–
150
mA
–
145
mA
LVPECL Output High Voltage V_DD = 3.3V or 2.5V, R_TERM = 50Ω to V_DD –1.15
–
V_DD – 2.0V
V_DD –0.75
V
LVPECL Output Low Voltage
V_DD = 3.3V or 2.5V, R_TERM = 50Ω to V_DD –2.0
V_DD – 2.0V
–
V_DD –1.625 V
LVPECL Peak-to-Peak Output V_DD = 3.3V or 2.5V, R_TERM = 50Ω to 600
–
1000
mV
Voltage Swing
V_DD – 2.0V
LVPECL Output Voltage Swing V_DD = 2.5V, R_TERM = 50Ω to V_DD –
500
–
1000
mV
(V_OH - V_OL)
1.5V
LVPECL Output Common Mode V_DD = 2.5V, R_TERM = 50Ω to V_DD –
1.2
–
Voltage (V_OH + V_OL)/2
1.5V
–
V
C_INX
Pin Capacitance, XIN & XOUT
4.5
pF
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. I_DD includes approximately 24 mA of current that is dissipated externally in the output termination resistors.
Document #: 001-52849 Rev. *A
Page 2 of 7
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