CY2XP21ZXC Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 125 MHz LVPECL Clock Generator

PRELIMINARY
CY2XP21
125 MHz LVPECL Clock Generator
Features
■ One LVPECL Output Pair
■ Output Frequency: 112 MHz to 140 MHz
■ External Crystal Frequency: 22.4 MHz to 28 MHz
■ Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal
(1.875 MHz to 20 MHz): 0.4 ps (Typical)
■ Pb-free 8-Pin TSSOP Package
■ Supply Voltage: 3.3V or 2.5V
■ Commercial and Industrial Temperature Ranges
Logic Block Diagram
Functional Description
The CY2XP21 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate a
125 MHz clock, which is ideal for 10 Gb Ethernet applications. It
also produces an output frequency that is five times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter. The CY2XP21
has a crystal oscillator interface input and one LVPECL output
pair.
E xt ernal
Cryst al
XIN
CR YS TAL
OSCILLATOR
X OU T
LOW -N OISE
PLL
OUTPU T
D IV IDE R
CLK
CLK#
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
VDD 1
VSS 2
XOUT 3
XIN 4
8
VDD
7
CLK
6
CLK#
5
NC
Table 1. Pin Definition - 8-Pin TSSOP
Pin Number Pin Name
1, 8
VDD
2
VSS
3, 4
XOUT, XIN
5
NC
I/O Type
Power
Power
XTAL output and input
6,7
CLK#, CLK
LVPECL output
Description
3.3V or 2.5V power supply
Ground
Parallel resonant crystal interface
No Connect
Differential Clock Output
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-52849 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 15, 2009
[+] Feedback