CY28354-400 Datasheet, PDF (2/9 Pages) SpectraLinear Inc – 210 MHz 24 Output Buffer for 4-DDR DIMMS for VIA Chipsets Support

CY28354-400
Pin Description
Pin
11, 13, 19, 21, 38, 36,
5, 7, 44, 42, 32, 30
12, 14, 20, 22, 37, 35,
6, 8, 43, 41, 31, 29
18,
4
17,
3
45
Name
PWR
DDRA[0:5]T VDD2.5
DDRB[0:5]T
DDRA[0:5]C VDD2.5
DDRB[0:5]C
BUF_INA, VDD2.5
BUF_INB
FB_OUTA VDD2.5
FB_OUTB
I2C_CS
VDD2.5
46
ADDR_SEL VDD2.5
25
SCLK
VDD2.5
26
SDATA
VDD2.5
1, 10, 16, 23, 28, 33, 39, 48 VDD2.5
2, 9, 15, 24, 27, 34, 40, 47 GND
I/O
Description
O Clock outputs. These outputs provide copies of BUF_INA and
BUF_INB, respectively.
O Clock outputs. These outputs provide complementary copies of
BUF_INA and BUF_INB, respectively.
I Reference input from chipset. 2.5V input. Internal pull-down
PD
O Feedback clock for chipset.
I CS for I2C allows for multiple devices to be connected with
PD the same I2C address. Internal pull-down. See Table 1.
I Selects I2C Address D2/DC. Internal Pull-down
PD
I SMBus clock input. Internal Pull-up
PU
I/O SMBus data input. Internal Pull-up
PU
2.5V voltage supply
Ground
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled. The registers associated with the Serial Data
Interface initializes to their default setting upon power-up, and
therefore use of this interface is optional. Clock device register
changes are normally made upon system initialization, if any
are required. The interface can also be used during system
operation for power management functions.
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1. The Block Write and Block Read
protocol is outlined in Table 2.The slave receiver address is
D2/DC depending on the state of the ADDRSEL pin.
Table 1. Command Code Definition
Bit
7
(6:5)
(4:0)
Description
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
01 to address chip when I2C_CS = 0
10 to address chip when I2C_CS = 1
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should
be '00000'
Document #: 38-07615 Rev. *B
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