CY26114 Datasheet, PDF (2/5 Pages) Cypress Semiconductor – One-PLL Clock Generator

CY26114
Pin Definitions
Name
XIN
V_DD
AV_DD
FS0
AV_SS
V_SSL
LCLK1
LCLK2
N/C
FS1
V_DDL
N/C
VSS
CLK3
CLK4
XOUT
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
Reference Crystal Input
Voltage Supply
Analog Voltage Supply
Frequency Select 0
Analog Ground
LCLK Ground
100-MHz output clock at V_DDL Level
100-MHz output clock at V_DDL Level
No Connect
Frequency Select 1
LCLK Voltage Supply (2.5V or 3.3V)
No Connect
Ground
50-MHz output clock
25/33/50/66-MHz clock output (frequency selectable)
Reference Crystal Output
Absolute Maximum Conditions
Parameter
V_DD
V_DDL
T_J
Description
Supply Voltage
I/O Supply Voltage
Junction Temperature
Digital Inputs
Digital Outputs referred to V_DD
Digital Outputs referred to V_DDL
Electro-Static Discharge
Min.
–0.5
AV_SS – 0.3
V_SS – 0.3
V_SS – 0.3
2
Max.
7.0
7.0
125
AV_DD + 0.3
V_DD + 0.3
V_DDL +0.3
Recommended Operating Conditions
Parameter
Description
V_DD
V_DDL
T_A
C_LOAD
f_REF
t_PU
Operating Voltage
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Reference Frequency
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be
monotonic)
Note:
1. Float XOUT if XIN is externally driven.
Min.
3.0
2.375
0
0.05
Typ.
3.3
2.5
25
Max.
3.6
2.625
70
15
500
Unit
V
V
°C
V
V
V
kV
Unit
V
V
°C
pF
MHz
ms
Document #: 38-07098 Rev. *A
Page 2 of 5