CY26114 Datasheet, PDF (1/5 Pages) Cypress Semiconductor – One-PLL Clock Generator

CY26114
One-PLL Clock Generator
Features
• Integrated phase-locked loop
• Low skew, low jitter, high accuracy outputs
• 3.3V Operation with 2.5 V Output Option
Part Number Outputs
CY26114
4
Input Frequency
25MHz Crystal Input
Benefits
Internal PLL with up to 333 MHz internal operation
Meets critical timing requirements in complex system designs
Enables application compatibility
Output Frequency Range
2 copies of 100MHz, 1 copy of 50MHz,
1 copy 25/33/50/66MHz (frequency selectable)
Logic Block Diagram
XIN
XOUT
OSC.
Q
Φ
VCO
P
PLL
OUTPUT
MULTIPLEXER
AND
DIVIDERS
FS0
FS1
VDDL
VDD AVDD AVSS VSS ^VSSL
Pin Configurations
100MHz
100MHz
50MHz
25/33/50/66MHz
(frequency selectable)
16-pin TSSOP
XIN ¹
VDD 2
AVDD 3
FS0 4
AVSS 5
VSSL 6
LCLK1 7
LCLK2 8
16 ^XOUT
15 CLK4
14 CLK3
13 VSS
12 _N/C
11 VDDL
10 _FS1
9 _N/C
CLK4 Frequency Select Options
FS1
FS0
0
0
0
1
1
0
1
1
CLK 4
25
33
50
66
Units
MHz
MHz
MHz
MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07098 Rev. *A
Revised December 14, 2002