CY24212_05 Datasheet, PDF (2/6 Pages) Cypress Semiconductor – MediaClock™ MPEG Clock Generator with VCXO

PRELIMINARY
CY24212
Pin Description
Name
Pin Number
XIN
1
VDD
2
VCXO
3
VSS
4
CLKA
5
FSEL (-1,-2)
6
FSEL (-3,-5)
6
VSS (-1)
7
CLKB (-2)
7
CLKB (-3,-5)
7
XOUT^[1]
8
Description
Reference Input.
Voltage Supply.
Input Analog Control for VCXO.
Ground.
27-MHz Clock Output.
Input Frequency Select, Weak Internal Pull-up.
FSEL = 0, XIN = 13.5 MHz
FSEL = 1, XIN = 27 MHz
Output Frequency Select, Weak Internal Pull-up.
FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz
FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz
Ground.
27 MHz.
27 MHz/27.027 MHz.
Reference Output.
Pullable Crystal Specifications
Parameter
CR_load
C0/C1
ESR
T_o
Crystal Accuracy
TT_s
Name
Crystal Load Capacitance
Equivalent Series Resistance
Operating Temperature
Crystal Accuracy
Stability over Temperature and Aging
Absolute Maximum Conditions
Parameter
V_DD
T_S
T_J
Description
Supply Voltage
Storage Temperature^[2]
Junction Temperature
Digital Inputs
Electrostatic Discharge
Min.
0
Min.
–0.5
–65
V_SS – 0.3
2
Typ.
Max.
14
240
35
50
70
± 20
± 50
Max.
7.0
125
125
V_DD + 0.3
Recommended Operating Conditions
Parameter
Description
V_DD
Operating Voltage
T_A
Ambient Temperature
C_LOAD
Max. Load Capacitance
f_REF
Reference Frequency
Notes:
1. Float XOUT if XIN is externally driven.
2. Rated for ten years.
Min.
3.135
0
13.5
Typ.
3.3
Max.
3.465
70
15
27
Unit
pF
Ω
°C
ppm
ppm
Unit
V
°C
°C
V
kV
Unit
V
°C
pF
MHz
Document #: 38-07402 Rev. *C
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