CY24212_05 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – MediaClock™ MPEG Clock Generator with VCXO

Features
• Integrated phase-locked loop (PLL)
• Low jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
PRELIMINARY
CY24212
MediaClock™
MPEG Clock Generator with VCXO
Benefits
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Enables application compatibility
Part Number
CY24212-1
CY24212-2
CY24212-3
CY24212-5
Outputs
1
2
2
2
Input Frequency Range
13.5 MHz/27 MHz (selectable)
13.5 MHz/27 MHz (selectable)
27 MHz
27 MHz
Output Frequencies
27 MHz
Two copies of 27 MHz
27 MHz/27.027 MHz (-1 ppm)
27 MHz/27.027 MHz (0 ppm)
Logic Block Diagram
XIN
XOUT
VCXO
OSC
FSEL
Q
Φ
VCO
P
PLL
VDD VSS
OUTPUT
DIVIDERS
CLKA (27 MHz)
27 MHz (-2)
27/27.027 MHz (-3)
Pin Configurations
CY24212-1
8-pin SOIC
XIN ¹
VDD ²
VCXO 3
VSS 4
8
XOUT
7
VSS
6
FSEL
5
CLKA 27 MHz
CY24212-2
8-pin SOIC
XIN ¹
VDD ²
VCXO 3
VSS 4
8
XOUT
7
CLKB 27 MHz
6
FSEL
5
CLKA 27 MHz
CY24212-3,-5
8-pin SOIC
XIN ¹
VDD ²
VCXO 3
VSS 4
8
XOUT
7
CLKB (27/27.027 MHz)
6
FSEL
5
CLKA 27 MHz
Table 1. CY24212 (-1, -2) Frequency Select Option
FSEL
0
1
Reference
13.5 MHz
27 MHz
CLKA/CLKB
27 MHz
27 MHz
Table 2. CY24212 (-3, -5) Frequency Select Option
FSEL
0
1
Reference
27 MHz
27 MHz
CLKA
27 MHz
27 MHz
CLKB
27 MHz
27.027 MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07402 Rev. *C
Revised April 6, 2005