CY23020-1 Datasheet, PDF (2/10 Pages) Cypress Semiconductor – 20-output, 200-MHz Zero Delay Buffer

CY23020-1
Pin Definitions^[2]
Pin Name
Pin No.
TSSOP
QFN
Pin
Type
Pin Description
REF+
REF–
45
39
I Reference Inputs: Output signals are synchronized to the crossing point of
46
40
REF+ and REF– signals. Therefore REF– must be tied to VREF as defined in
the DC characteristics table. In DC mode, the REF+/REF– inputs must be held
at opposite logical states. For optimal performance, the impedances seen by
these two inputs must be equal.
FBIN+
FBIN–
4
46
I Feedback Inputs: Input FBIN+ must be fed by one of the outputs to ensure
3
45
proper functionality. If the trace between FBIN+ and FBOUT is equal in length
to the traces between the outputs and the signal destinations, then the signals
received at the destinations will be synchronized to the clock signal at REF+
input.
FBIN– must be tied to VREF as defined in the DC characteristics table. In DC
mode, FBIN+/FBIN– inputs must be held at opposite logical states. For best
performance, the impedances seen by these two inputs must be equal.
FBOUT
6
48
O Feedback Output: In order to complete the phase locked loop, an output must
be connected back to the FBIN+ pin. Any of the outputs may actually be used
as the feedback source.
Q1:19
RANGE¹
7, 9, 10, 12, 1,3,4,6,7,9,1 O Outputs: Refer to Tables 1–4 for the configuration of these outputs.
13, 15, 16, 0,12,13,24,2
18, 19, 30, 5,27,28,30,3
31, 33, 34, 1,33,34,36,3
36, 37, 39,
7
40, 42, 43
24
18
I Frequency Range Selection Input: To determine the correct connection for
this pin, refer to Table 2. This should be a static input
LOCK
1
43
O PLL Locked Output: When this output is HIGH, the PLL in the CY23020-1 is
in steady state operation mode (Locked). When this signal is LOW, the PLL
is in the process of locking onto the reference signal.
S1:2
22, 21
16,15
I Output/PLL Enable Selection bits: To determine appropriate settings, refer
to Table 1.
VDD
5,11,26, 32 P Power Connection
VDDC
27, 48
21, 42
P Analog Power Connection: Connect to 3.3V.
GNDC
28, 47
G Analog Ground Connection: Connect to common system ground plane.
VDD
5, 11, 17, 32,
38, 44
38,47
P Output Buffer Power Connections: Connect to 2.5 or 3.3V, whichever is to
be the reference for the output signals.
GND
8, 14, 20, 25,
19
29, 35, 41
G Ground Connections: Connect to common system ground plane.
VSS
2,8,14,23,29 G Ground Connections
,35
VSSC
MUL^[1]
C1^[1]
22,41
G Ground Connections
23
17
I Multiplication Factor Select: When set HIGH, the outputs will run at twice
the speed of the reference signal. This should be a static input
26
20
I Output Configuration Bit: Establishes either 2.5V or 3.3V Full Swing
Operation. To determine appropriate setting, refer to Table 3. This should be
a static input
NC
2
44
NC Do Not Connect: This pin must be left floating. This pin is used by the factory
for testing purposes.
Note:
1. RANGE and MUL have a ~100k pull-down. C1 has a 50k pull-down. These inputs (RANGE, MUL, C1) are static.
2. There are no power-up sequence requirements on the power supply pins of the CY23020-1.
Document #: 38-07120 Rev. *B
Page 2 of 10