CY23020-1 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 20-output, 200-MHz Zero Delay Buffer

CY23020-1
20-output, 200-MHz Zero Delay Buffer
Features
• 335 ps max Total Timing Budget™ (TTB)™ window
• 2.5V or 3.3V outputs
• 20 LVCMOS outputs
• 50 MHz to 200 MHz output frequency
• 50 MHz to 200 MHz input frequency
• Integrated phase-locked loop (PLL) with lock indicator
• Spread Aware™—designed to work with SSFTG
reference signals
• 3.3V core power supply
• Available in 48-pin TSSOP and QFN packages
Block Diagram
LOCKED
REF
FBIN
Div
PLL
FBOUT
Q1
Q2
C1
S1:2
C1
C1C1
RANGE
MUL
Output
Control
Logic
Q17
Q18
Q19
1 Q1
2 VSS
3 Q2
4 Q3
5
VDD
6
Q4
7 Q5
8 VSS
9
Q6
10 Q7
11 VDD
12 Q8
48
47
46
45
44
43
F
V
F
F
N
L
B
D
B
B
C
O
O
D
I
I
C
U
N
N
K
T
+
-
+
42
41
40
V
V
R
D
S
E
D
S
F
C
C
-
4 8 -p in Q F N
Q
V
9
S
S
2
S
M
R
1
U
A
L
N
S
G
E
13
14
15
16
17
18
G
C
V
N
1
D
D
D
C
19
20
21
Description
The CY23020-1-1 is a high-performance 200-MHz PLL-based
zero delay buffer designed for high-speed clock distribution
applications. The device features a guaranteed TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
The CY23020-1 outputs are three-state when S1 = S2 = 0 for
reduced power. When S1 = 1 and S2 = 0 the PLL is bypassed
and the CY23020-1 functions as a fan-out buffer.
Pin Configurations
39
38
37
R
V
Q
E
D
1
F
D
9
+
V
S
S
C
V
S
S
Q
1
0
22
23
24
Q 18 36
VSS 35
Q 17 34
Q 16 33
VDD 32
Q 15 31
Q 14 30
VSS 29
Q 13 28
Q 12 27
VDD 26
Q 11 25
LOCK
1
NC
2
FBIN–
3
FBIN+
4
VDD
5
FBOUT
6
Q1
7
GND
8
Q2
9
Q3
10
VDD
11
Q4
12
Q5
13
GND
14
Q6
15
Q7
16
VDD
17
Q8
18
Q9
19
GND
20
S2
21
S1
22
MUL
23
RANGE
24
48
VDDC
47
GNDC
46
REF–
45
REF+
44
VDD
43
Q19
42
Q18
41
GND
40
Q17
39
Q16
38
VDD
37
Q15
36
Q14
35
GND
34
Q13
33
Q12
32
VDD
31
Q11
30
Q10
29
GND
28
GNDC
27
VDDC
26
C1
25
GND
48-pin TSSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07120 Rev. *B
Revised November 5, 2002