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CY7C1480V33_07 Datasheet, PDF (19/32 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
Industrial –40°C to +85°C
to VDD
Electrical Characteristics Over the Operating Range[12, 13]
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
Power Supply Voltage
IO Supply Voltage
For 3.3V IO
For 2.5V IO
3.135
3.135
2.375
VOH
Output HIGH Voltage For 3.3V IO, IOH = –4.0 mA
For 2.5V IO, IOH = –1.0 mA
VOL
Output LOW Voltage For 3.3V IO, IOL = 8.0 mA
For 2.5V IO, IOL = 1.0 mA
VIH
Input HIGH Voltage[12] For 3.3V IO
For 2.5V IO
VIL
Input LOW Voltage[12] For 3.3V IO
For 2.5V IO
2.4
2.0
2.0
1.7
–0.3
–0.3
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
–5
except ZZ and MODE
Input Current of MODE Input = VSS
–30
Input = VDD
Input Current of ZZ
Input = VSS
–5
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
Current
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB1
Automatic CE
VDD = Max, Device Deselected,
4.0-ns cycle, 250 MHz
Power Down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB2
Automatic CE
VDD = Max, Device Deselected, VIN ≤ All speeds
Power Down
0.3V or VIN > VDDQ – 0.3V, f = 0
Current—CMOS Inputs
ISB3
Automatic CE
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
Power Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB4
Automatic CE
VDD = Max, Device Deselected,
All speeds
Power Down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Notes
12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
13. Power up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Max. Unit
3.6
V
VDD
V
2.625 V
V
V
0.4
V
0.4
V
VDD + 0.3V V
VDD + 0.3V V
0.8
V
0.7
V
5
µA
µA
5
µA
µA
30
µA
5
µA
500 mA
500 mA
450 mA
245 mA
245 mA
245 mA
120 mA
245 mA
245 mA
245 mA
135 mA
Document #: 38-05283 Rev. *H
Page 19 of 32
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