CY7C1480V33_07 Datasheet, PDF (14/32 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

CY7C1480V33
CY7C1482V33
CY7C1486V33
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
After the data is captured, the data can be shifted out by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
TAP Timing
1
2
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
3
4
5
6
Test Clock
(TCK )
Test M ode Select
(TM S)
tTH
tTL
tTM _SS tTM _SH
tCY _C
tTDIS tTDIH
Test Data-In
(TDI)
Test Data-Out
(TDO)
tTDOV
tTDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range^{[9, 10]}
Parameter
Description
Clock
t_TCYC
TCK Clock Cycle Time
t_TF
TCK Clock Frequency
t_TH
TCK Clock HIGH Time
t_TL
TCK Clock LOW Time
Output Times
t_TDOV
TCK Clock LOW to TDO Valid
t_TDOX
TCK Clock LOW to TDO Invalid
Setup Times
t_TMSS
TMS Setup to TCK Clock Rise
t_TDIS
TDI Setup to TCK Clock Rise
t_CS
Capture Setup to TCK Rise
Hold Times
t_TMSH
TMS Hold after TCK Clock Rise
t_TDIH
TDI Hold after Clock Rise
t_CH
Capture Hold after Clock Rise
Notes
9. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. t_R/t_F = 1 ns.
Min.
50
20
20
0
5
5
5
5
5
5
Max.
20
10
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05283 Rev. *H
Page 14 of 32
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