CY7C1386D_12 Datasheet, PDF (19/34 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM

Boundary Scan Order
165-ball BGA ^{[12, 13]}
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Ball ID
N6
N7
N10
P11
P8
R8
R9
P9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
CY7C1386D
CY7C1387D
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
Notes
12. Balls that are NC (No Connect) are preset LOW.
13. Bit#89 is preset HIGH.
Document Number: 38-05545 Rev. *J
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