CY7C1386D_12 Datasheet, PDF (1/34 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM

CY7C1386D
CY7C1387D
18-Mbit (512 K × 36/1 M × 18) Pipelined
DCD Sync SRAM
18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM
Features
■ Supports bus operation up to 200 MHz
■ Available speed grades are 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ Optimal for performance (double-cycle deselect)
■ Depth expansion without wait state
■ 3.3 V core power supply (V_DD)
■ 2.5 V or 3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 3 ns (for 200 MHz device)
■ Provides high performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel^ Pentium^
Interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ CY7C1386D available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1387D available in JEDEC-standard Pb-free
100-pin TQFP and non Pb-free 165-ball BGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ ZZ sleep mode option
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Functional Description
The CY7C1386D/CY7C1387D SRAM integrates
512 K × 36/1 M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE₁), depth expansion chip
enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP, and
ADV), write enables (BW_X, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Configurations on page 5 and Truth Table on
page 10 for further details). Write cycles can be one to four bytes
wide as controlled by the byte write control inputs. GW active
LOW causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off the
output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penalizing
system performance.
The CY7C1386D/CY7C1387D operates from a +3.3 V core
power supply while all outputs operate with a +3.3 V or +2.5 V
supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
200 MHz 167 MHz Unit
3.0
3.4
ns
300
275
mA
70
70
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05545 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 24, 2012