CY28551-3 Datasheet, PDF (19/29 Pages) Cypress Semiconductor – Universal Clock Generator for Intel, VIA and SIS®

CY28551-3
VDD_A = 2.0V
S0
Power Off
Figure 11. VTT_PWRGD# Timing Diagram
S1
Delay >
0.25 ms
VTT_PWRGD# = Low
S2
Sample
Inputs straps
VDD_A = off
S3
Normal
Operation
VTT_PWRGD# = toggle
Wait for <1.8 ms
Enable Outputs
Figure 12. VTT_PWRGD# Timing Diagram
FS_[D:A]
VTT_PWRGD#
PWRGD_VRM
VDD Clock Gen
Clock State State 0
0.2-0.3 ms
Delay
State 1
Wait for
VTT_PWRGD#
Sample Sels
State 2
Off
Clock Outputs
Off
On
Clock VCO
Device is not affected,
VTT_PWRGD# is ignored
State 3
On
Document #: 001-05677 Rev. *D
Page 19 of 29