CY7C1474V25 Datasheet, PDF (18/27 Pages) Cypress Semiconductor – 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

PRELIMINARY
CY7C1470V25
CY7C1472V25
CY7C1474V25
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V_DD Relative to GND........ –0.5V to +3.6V
DC to Outputs in Tri-State ................... –0.5V to V_DDQ + 0.5V
DC Input Voltage....................................–0.5V to V_DD + 0.5V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
Commercial 0°C to +70°C
V_DD
2.5V–5%/+5%
V_DDQ
1.7V to V_DD
Electrical Characteristics Over the Operating Range^{[12, 13]}
Parameter
Description
Test Conditions
Min.
V_DD
V_DDQ
V_OH
V_OL
V_IH
V_IL
I_X
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage^[12]
Input LOW Voltage^[12]
Input Load Current ex-
cept ZZ and MODE
V_DDQ = 2.5V
V_DDQ = 1.8V
V_DD = Min., I_OH= −1.0 mA, V_DDQ = 2.5V
V_DD = Min., I_OH = –100 µA,V_DDQ = 1.8V
V_DD = Min., I_OL= 1.0 mA, V_DDQ = 2.5V
V_DD = Min., I_OL= 100 µA,V_DDQ = 1.8V
V_DDQ = 2.5V
V_DDQ = 1.8V
V_DDQ = 2.5V
V_DDQ = 1.8V
GND ≤ V_I ≤ V_DDQ
2.375
2.375
1.7
2.0
1.6
1.7
1.26
–0.3
–0.3
–5
Input Current of MODE Input = V_SS
–5
Input = V_DD
Input Current of ZZ
Input = V_SS
–30
Input = V_DD
I_OZ
Output Leakage Current GND ≤ V_I ≤ V_DDQ, Output Disabled
–5
I_DD
V_DD Operating Supply V_DD = Max., I_OUT = 0 mA,
4.0-ns cycle, 250 MHz
f = f_MAX = 1/t_CYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
I_SB1
Automatic CE
Max. V_DD, Device Deselected, 4.0-ns cycle, 250MHz
Power-down
V_IN ≥ V_IH or V_IN ≤ V_IL, f = f_MAX = _{5.0-ns cycle, 200 MHz}
Current—TTL Inputs 1/t_CYC
6.0-ns cycle, 167 MHz
I_SB2
Automatic CE
Max. V_DD, Device Deselected, All speed grades
Power-down
V_IN ≤ 0.3V or V_IN > V_DDQ − 0.3V,
Current—CMOS Inputs f = 0
I_SB3
Automatic CE
Max. V_DD, Device Deselected, 4.0-ns cycle, 250 MHz
Power-down
V_IN ≤ 0.3V or V_IN > V_DDQ − 0.3V, _{5.0-ns cycle, 200 MHz}
Current—CMOS Inputs f = f_MAX = 1/t_CYC
6.0-ns cycle, 167 MHz
I_SB4
Automatic CE
Max. V_DD, Device Deselected, All speed grades
Power-down
V_IN ≥ V_IH or V_IN ≤ V_IL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
12. Overshoot: V_IH(AC) < V_DD +1.5V (Pulse width less than t_CYC/2), undershoot: V_IL(AC)> –2V (Pulse width less than t_CYC/2).
13. T_Power-up: Assumes a linear ramp from 0V to V_DD (min.) within 200 ms. During this time V_IH < V_DD and V_DDQ < V_DD.
Max.
2.625
V_DD
1.9
0.4
0.2
V_DD + 0.3V
V_DD + 0.3V
0.7
0.36
5
30
5
5
450
450
400
200
200
200
120
200
200
200
135
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Document #: 38-05290 Rev. *E
Page 18 of 27