CY7C1474V25 Datasheet, PDF (12/27 Pages) Cypress Semiconductor – 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

PRELIMINARY
CY7C1470V25
CY7C1472V25
CY7C1474V25
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
TAP Timing
1
2
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
3
4
5
6
Test Clock
(TCK)
Test Mode Select
(TMS)
tTH
tTL
tTMSS tTMSH
tCYC
tTDIS tTDIH
Test Data-In
(TDI)
Test Data-Out
(TDO)
tTDOV
tTDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range^{[9, 10]}
Parameter
Description
Clock
t_TCYC TCK Clock Cycle Time
t_TF
TCK Clock Frequency
t_TH
TCK Clock HIGH time
t_TL
TCK Clock LOW time
Output Times
t_TDOV TCK Clock LOW to TDO Valid
t_TDOX TCK Clock LOW to TDO Invalid
Set-up Times
t_TMSS TMS Set-up to TCK Clock Rise
t_TDIS TDI Set-up to TCK Clock Rise
t_CS
Capture Set-up to TCK Rise
Hold Times
t_TMSH TMS hold after TCK Clock Rise
t_TDIH TDI Hold after Clock Rise
t_CH
Capture Hold after Clock Rise
Notes:
9. t_CS and t_CH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. t_R/t_F = 1 ns.
Min.
50
25
25
0
5
5
5
5
5
5
Max.
20
5
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05290 Rev. *E
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