CY7C09449PVA-AC Datasheet, PDF (18/52 Pages) Cypress Semiconductor – 128 Kb Dual-Port SRAM with PCI Bus Controller

CY7C09449PVA-AC
Basic 8-Bit Interface
Figure 5 and Figure 6 illustrate the operation of the 8-bit interface mode. Note that only data lines DQ[7:0] are used. DQ[31:8] are not
used and must be tied high or low; they cannot be left floating. The least significant bits of the local address, A[1] and A[0], must be
connected to the byte enable pins BE[3] and BE[2], respectively. These must be valid during the address phase.
In burst operation, BE#[3:2] are inputs used at A1 and A0 of the local address bus. Bursts to the 8-bit interface do not need to start
on a DWORD boundary. The internal DWORD address automatically increments after a data phase where BE[3:2] equals '11',
(A[1:0] = '11').
Figure 5. Single Cycle Operation
ASMODE= '00', RWMODE= '00', BW =' 00', DDOUT = '0'
CLKIN
Single Data Read
~
Single Data Write
STROBE
~
SELECT#
~
READ#
~
WRITE#
~
(not used)
RDY_IN#
~
RDY_IN
~
RDY_OUT#
BLAST#
ADR[14:2]
Valid
BE#[3:2]
Valid
BE#[1]
(hniogthu) sed)
BE#[0]
DQ[7:0]
BOLD indicates output
from PCI-DP
DATA OUT
PCI-DP drives
DQ bus here
~
~
~
Valid
~
Valid
~
~
~
DATA IN
WAV6A.VSD 9/11/
Document #: 001-40319 Rev. *B
Page 18 of 52
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