CY7C09449PVA-AC Datasheet, PDF (1/52 Pages) Cypress Semiconductor – 128 Kb Dual-Port SRAM with PCI Bus Controller

CY7C09449PVA-AC
128 Kb Dual-Port SRAM with PCI Bus
Controller (PCI-DP)
Features
Functional Overview
■ 128 Kb of dual-ported shared memory
■ Master and target PCI Specification 2.2 compliant interface
■ Embedded host bridge capability
■ Direct interface to many microprocessors
■ I₂O message transport unit; includes four 32-bit, 32 entry FIFO
■ Local bus clock rates up to 50 MHz
■ Single 3.3V power supply including compatibility with 3V and
5V PCI bus signaling
■ 160-pin thin plastic quad flat package
Introduction
The CY7C09449PVA is one of the PCI interface controllers in the
Cypress Semiconductor PCI-DP™ family. The CY7C09449PVA
provides a PCI master and target interface with direct
connections to many popular microprocessors. It provides 128
Kb of dual-port SRAM that is used as shared memory between
the local microprocessor and the PCI bus. An I₂O message unit,
complete with message queues and interrupt capability, is also
provided. The CY7C09449PVA allows the designer to interface
an application to the PCI bus in a straightforward and
inexpensive way.
Logic Block Diagram
The CY7C09449PVA is composed of several shared resources
that allow effective data movement between the local bus and
the PCI bus.
A primary resource within the CY7C09449PVA is its 128 Kb of
dual-port memory. This memory is interfaced to both the PCI bus
and a local microprocessor bus. This shared memory is
accessed as a target from both buses at the same time for inter
process communication. The CY7C09449PVA is directed from
both the local and PCI bus to become a PCI bus master and
move data into or out of the internal shared memory as a direct
memory access (DMA). The CY7C09449PVA can DMA across
the PCI bus any number of 32-bit double words (DWORD), up to
16K bytes. It uses the full bursting capabilities of the PCI bus for
maximum efficiency and transfers data over the full 32-bit PCI
address space.
The CY7C09449PVA implements optional requirements of the
PCI specification by selecting the optimum PCI command for
each transaction it masters to the PCI bus. This maximizes the
overall efficiency of the system platform. PCI bridging functions
(PCI-to-PCI and Host-to-PCI bridges) use the commands to
enhance prefetch and cache coherency operations. The
CY7C09449PVA requests and gains access to the PCI bus as
any master. It does not include a PCI bus arbitration function.
Standard PC PCI buses include this function; embedded
systems may need to implement this function.
The CY7C09449PVA provides a direct access mechanism from
the local bus to the PCI bus. With it, the local processor directs
the CY7C09449PVA to run a PCI bus master cycle of any kind
to any address. This means that the CY7C09449PVA runs PCI
configuration cycles as a host bridge.
Bus Master/Slave
Interface
Up to 16 KByte Burst
Transfers on PCI Bus
User-Configurable Target Interface
(Supports Burst Mode)
PCI Bus
128 Kb Dual-Port
Shared Memory
I₂O Message
Transport Unit
Operations
Registers
Local Bus
I²C SCL/SDA
PCI-DPTM Allows Local Processor
Direct Access to PCI Bus
Provides Required FIFOs and
Interrupt Status Registers
AN3042_BD.vsd
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-40319 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 07, 2009
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