CY14B512Q1 Datasheet, PDF (18/27 Pages) Cypress Semiconductor – 512-Kbit (64 K × 8) Serial (SPI) nvSRAM

CY14B512Q1
CY14B512Q2
CY14B512Q3
AC Switching Characteristics
Cypress
Parameter
f_SCK
t_CL
t_CH
t_CS
t_CSS
t_CSH
t_SD
t_HD
t_HH
t_SH
t_CO
t_HHZ[8]
t_HLZ[8]
t_OH
t_HZCS
f_SCK
t_WL
t_WH
t_CE
t_CES
t_CEH
t_SU
t_H
t_HD
t_CD
t_V
t_HZ
t_LZ
t_HO
t_DIS
Alt.
Parameter
Description
Clock frequency, SCK
Clock pulse width lOW
Clock pulse width HIGH
CS high time
CS setup time
CS hold time
Data in setup time
Data in hold time
HOLD hold time
HOLD setup time
Output valid
HOLD to output high Z
HOLD to output low Z
Output hold time
Output disable time
Figure 21. Synchronous Data Timing (Mode 0)
CS
SCK
SI
tCSS
tCH
tSD
tHD
VALID IN
HI-Z
SO
CS
tCL
tCO
Figure 22. HOLD Timing
40 MHz
Min
Max
–
40
11
–
11
–
20
–
10
–
10
–
5
–
5
–
5
–
5
–
–
9
–
15
–
15
0
–
–
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCS
tCSH
tOH
tHZCS
HI-Z
SCK
HOLD
SO
tHH
tSH
tHHZ
Note
8. These parameters are guaranteed by design and are not tested.
Document #: 001-53873 Rev. *E
tHH
tSH
tHLZ
Page 18 of 27
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