CY14B256K_09 Datasheet, PDF (18/28 Pages) Cypress Semiconductor – 256 Kbit (32K x 8) nvSRAM with Real Time Clock

CY14B256K
AC Switching Characteristics (continued)
Parameter
Cypress
Alt.
Parameter Parameter
SRAM Write Cycle
t_WC
t_PWE
t_SCE
t_SD
t_HD
t_AW
t_SA
t_HA
t_HZWE ^{[12, 15]}
t_LZWE ^[12]
t_AVAV
t_WLWH, t_WLEH
t_ELWH, t_ELEH
t_DVWH, t_DVEH
t_WHDX, t_EHDX
t_AVWH, t_AVEH
t_AVWL, t_AVEL
t_WHAX, t_EHAX
t_WLQZ
t_WHQX
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
25 ns
Min Max
25
20
20
10
0
20
0
0
10
3
35 ns
Min Max
35
25
25
12
0
25
0
0
13
3
Figure 10. SRAM Write Cycle 1: WE Controlled ^{[14, 16]}
ADDRESS
tWC
CE
WE
tSCE
tHA
tAW
tSA
tPWE
45 ns
Unit
Min Max
45
ns
30
ns
30
ns
15
ns
0
ns
30
ns
0
ns
0
ns
15
ns
3
ns
DATA IN
DATA OUT
ADDRESS
PREVIOUS DATA
tHZWE
tSD
tHD
DATA VALID
HIGH IMPEDANCE
Figure 11. SRAM Write Cycle 2: CE Controlled
tWC
tLZWE
tSA
tSCE
tHA
CE
WE
DATA IN
tAW
tPWE
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Notes
15. If WE is Low when CE goes Low, the outputs remain in the High Impedance State.
16. CE or WE are greater than V_IH during address transitions.
Document Number: 001-06431 Rev. *H
Page 18 of 28
[+] Feedback